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Mon, 19 Feb 2024 00:32:55 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Subject: [PULL 40/49] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines Date: Mon, 19 Feb 2024 18:29:29 +1000 Message-ID: <20240219082938.238302-41-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240219082938.238302-1-npiggin@gmail.com> References: <20240219082938.238302-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=npiggin@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1708331781249100003 Wire the ChipTOD model to powernv9 and powernv10 machines. Suggested-by-by: C=C3=A9dric Le Goater Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/pnv.c | 30 ++++++++++++++++++++++++++++++ include/hw/ppc/pnv_chip.h | 3 +++ 2 files changed, 33 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index acc4db00c1..8beddb1313 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1427,6 +1427,8 @@ static void pnv_chip_power9_instance_init(Object *obj) =20 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); =20 + object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHI= PTOD); + object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); =20 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); @@ -1573,6 +1575,19 @@ static void pnv_chip_power9_realize(DeviceState *dev= , Error **errp) chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", (uint64_t) PNV9_LPCM_BASE(chip= )); =20 + /* ChipTOD */ + object_property_set_bool(OBJECT(&chip9->chiptod), "primary", + chip->chip_id =3D=3D 0, &error_abort); + object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", + chip->chip_id =3D=3D 1, &error_abort); + object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), + &error_abort); + if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, + &chip9->chiptod.xscom_regs); + /* Create the simplified OCC model */ if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { return; @@ -1685,6 +1700,8 @@ static void pnv_chip_power10_instance_init(Object *ob= j) "xive-fabric"); object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); + object_initialize_child(obj, "chiptod", &chip10->chiptod, + TYPE_PNV10_CHIPTOD); object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER= ); @@ -1820,6 +1837,19 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", (uint64_t) PNV10_LPCM_BASE(chi= p)); =20 + /* ChipTOD */ + object_property_set_bool(OBJECT(&chip10->chiptod), "primary", + chip->chip_id =3D=3D 0, &error_abort); + object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", + chip->chip_id =3D=3D 1, &error_abort); + object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip= ), + &error_abort); + if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, + &chip10->chiptod.xscom_regs); + /* Create the simplified OCC model */ if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { return; diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 9b06c8d87c..af4cd7a8b8 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -2,6 +2,7 @@ #define PPC_PNV_CHIP_H =20 #include "hw/pci-host/pnv_phb4.h" +#include "hw/ppc/pnv_chiptod.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" #include "hw/ppc/pnv_n1_chiplet.h" @@ -79,6 +80,7 @@ struct Pnv9Chip { PnvXive xive; Pnv9Psi psi; PnvLpcController lpc; + PnvChipTOD chiptod; PnvOCC occ; PnvSBE sbe; PnvHomer homer; @@ -111,6 +113,7 @@ struct Pnv10Chip { PnvXive2 xive; Pnv9Psi psi; PnvLpcController lpc; + PnvChipTOD chiptod; PnvOCC occ; PnvSBE sbe; PnvHomer homer; --=20 2.42.0