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Sun, 18 Feb 2024 17:18:15 -0800 (PST) From: Sergey Kambalin X-Google-Original-From: Sergey Kambalin To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Sergey Kambalin Subject: [PATCH v5 26/41] Implement GENET MDIO Date: Sun, 18 Feb 2024 19:17:24 -0600 Message-Id: <20240219011739.2316619-27-sergey.kambalin@auriga.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219011739.2316619-1-sergey.kambalin@auriga.com> References: <20240219011739.2316619-1-sergey.kambalin@auriga.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::112e; envelope-from=serg.oker@gmail.com; helo=mail-yw1-x112e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1708305957862100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Sergey Kambalin --- hw/net/bcm2838_genet.c | 126 ++++++++++++++++++++++++++++++++- include/hw/net/bcm2838_genet.h | 3 +- 2 files changed, 126 insertions(+), 3 deletions(-) diff --git a/hw/net/bcm2838_genet.c b/hw/net/bcm2838_genet.c index 56ff6a6f39..1fae3ecbc2 100644 --- a/hw/net/bcm2838_genet.c +++ b/hw/net/bcm2838_genet.c @@ -213,6 +213,7 @@ FIELD(GENET_PHY_STAT_1000, LOCALRXOK, 13, 1) FIELD(GENET_PHY_STAT_1000, MSRES, 14, 1) FIELD(GENET_PHY_STAT_1000, MSFAIL, 15, 1) =20 +/* There are two data representations for PHY_AUX_CTRL register */ REG16(GENET_PHY_AUX_CTRL_0, 0) FIELD(GENET_PHY_AUX_CTRL_0, REG_ID_MASK, 0, 3) FIELD(GENET_PHY_AUX_CTRL_0, RSVD_3, 3, 1) @@ -269,6 +270,123 @@ static void bcm2838_genet_set_irq_prio(BCM2838GenetSt= ate *s) qemu_set_irq(s->irq_prio, level); } =20 +static void bcm2838_genet_phy_aux_ctl_write(BCM2838GenetState *s, + uint16_t value) +{ + uint16_t reg_id =3D FIELD_EX16(value, GENET_PHY_AUX_CTRL_0, REG_ID); + uint16_t reg_id_mask =3D FIELD_EX16(value, GENET_PHY_AUX_CTRL_0, REG_I= D_MASK); + uint16_t misc_wren =3D FIELD_EX16(value, GENET_PHY_AUX_CTRL_0, MISC_WR= EN); + uint16_t reg_data =3D FIELD_EX16(value, GENET_PHY_AUX_CTRL_0, REG_DATA= ); + uint16_t reg_data12 =3D FIELD_EX16(value, GENET_PHY_AUX_CTRL_1, REG_DA= TA); + + uint16_t *phy_aux_ctl_shd_reg_id =3D (uint16_t *)&s->phy_aux_ctl_shd_r= egs + reg_id; + uint16_t *phy_aux_ctl_shd_reg_id_mask =3D (uint16_t *)&s->phy_aux_ctl_= shd_regs + reg_id_mask; + + if (reg_id_mask =3D=3D BCM2838_GENET_PHY_AUX_CTL_MISC) { + if (reg_id =3D=3D BCM2838_GENET_PHY_AUX_CTL_MISC) { + if (misc_wren =3D=3D 0) { + /* write for subsequent read (8-bit from AUX_CTL_MISC) */ + FIELD_DP16(value, GENET_PHY_AUX_CTRL_0, REG_DATA, *phy_aux= _ctl_shd_reg_id); + } else { + /* write 8 bits to AUX_CTL_MISC */ + *phy_aux_ctl_shd_reg_id_mask =3D reg_data; + } + } else { + /* write for subsequent read (12-bit) */ + FIELD_DP16(value, GENET_PHY_AUX_CTRL_1, REG_DATA, *phy_aux_ctl= _shd_reg_id); + } + } else { + /* write 12 bits */ + *phy_aux_ctl_shd_reg_id_mask =3D reg_data12; + } + + s->phy_regs.aux_ctl =3D value; +} + +static void bcm2838_genet_phy_shadow_write(BCM2838GenetState *s, + uint16_t value) +{ + uint16_t reg_id =3D FIELD_EX16(value, GENET_PHY_SHADOW, REG_ID); + uint16_t wr =3D FIELD_EX16(value, GENET_PHY_SHADOW, WR); + uint16_t reg_data =3D FIELD_EX16(value, GENET_PHY_SHADOW, REG_DATA); + + uint16_t *phy_shd_reg =3D (uint16_t *)&s->phy_shd_regs + reg_id; + + if (wr =3D=3D 0) { + FIELD_DP16(value, GENET_PHY_SHADOW, REG_DATA, *phy_shd_reg); + } else { + *phy_shd_reg =3D reg_data; + } + + s->phy_regs.shd =3D value; +} + +static void bcm2838_genet_phy_exp_shadow_write(BCM2838GenetState *s, + uint16_t value) +{ + /* TODO Stub implementation without side effect, + just storing registers values */ + uint16_t reg_id =3D FIELD_EX16(s->phy_regs.exp_ctrl, + GENET_PHY_EXP_SEL, REG_ID); + uint16_t block_id =3D FIELD_EX16(s->phy_regs.exp_ctrl, + GENET_PHY_EXP_SEL, BLOCK_ID); + + s->phy_exp_shd_regs.regs[block_id][reg_id] =3D value; +} + +static uint16_t bcm2838_genet_phy_exp_shadow_read(BCM2838GenetState *s) +{ + uint16_t reg_id =3D FIELD_EX16(s->phy_regs.exp_ctrl, + GENET_PHY_EXP_SEL, REG_ID); + uint16_t block_id =3D FIELD_EX16(s->phy_regs.exp_ctrl, + GENET_PHY_EXP_SEL, BLOCK_ID); + + return s->phy_exp_shd_regs.regs[block_id][reg_id]; +} + +static uint64_t bcm2838_genet_mdio_cmd(BCM2838GenetState *s, uint64_t cmd) +{ + uint32_t phy_reg_id =3D FIELD_EX32(cmd, GENET_UMAC_MDIO_CMD, REG_ID); + uint32_t phy_reg_data =3D FIELD_EX32(cmd, GENET_UMAC_MDIO_CMD, REG_DAT= A); + uint32_t start_busy =3D FIELD_EX32(cmd, GENET_UMAC_MDIO_CMD, START_BUS= Y); + uint32_t rd =3D FIELD_EX32(cmd, GENET_UMAC_MDIO_CMD, RD); + uint32_t wr =3D FIELD_EX32(cmd, GENET_UMAC_MDIO_CMD, WR); + uint16_t *phy_reg =3D (uint16_t *)&s->phy_regs + phy_reg_id; + + uint16_t anrestart =3D FIELD_EX16(phy_reg_data, GENET_PHY_BMCR, ANREST= ART); + + if (start_busy !=3D 0) { + cmd =3D FIELD_DP32(cmd, GENET_UMAC_MDIO_CMD, START_BUSY, 0); + + if (rd !=3D 0) { + if (phy_reg_id =3D=3D BCM2838_GENET_EXP_DATA) { + cmd =3D FIELD_DP32(cmd, GENET_UMAC_MDIO_CMD, REG_DATA, + bcm2838_genet_phy_exp_shadow_read(s)); + } else { + cmd =3D FIELD_DP32(cmd, GENET_UMAC_MDIO_CMD, REG_DATA, *ph= y_reg); + } + } else if (wr !=3D 0) { + if (phy_reg_id =3D=3D BCM2838_GENET_PHY_AUX_CTL) { + bcm2838_genet_phy_aux_ctl_write(s, phy_reg_data); + } else if (phy_reg_id =3D=3D BCM2838_GENET_PHY_SHD) { + bcm2838_genet_phy_shadow_write(s, phy_reg_data); + } else if (phy_reg_id =3D=3D BCM2838_GENET_EXP_DATA) { + bcm2838_genet_phy_exp_shadow_write(s, phy_reg_data); + } else { + if (phy_reg_id =3D=3D BCM2838_GENET_PHY_BMCR) { + /* Initiate auto-negotiation once it has been restarte= d */ + if (anrestart =3D=3D 1) { + FIELD_DP16(phy_reg_data, GENET_PHY_BMCR, ANRESTART= , 0); + } + } + *phy_reg =3D phy_reg_data; + } + } + } + + return cmd; +} + static uint64_t bcm2838_genet_read(void *opaque, hwaddr offset, unsigned s= ize) { uint64_t value =3D ~0; @@ -353,10 +471,13 @@ static void bcm2838_genet_write(void *opaque, hwaddr = offset, uint64_t value, trace_bcm2838_genet_mac_address(ncs->info_str); break; case BCM2838_GENET_UMAC_MDIO_CMD: + value =3D bcm2838_genet_mdio_cmd(s, value); + s->regs.intrl0.stat =3D FIELD_DP32(s->regs.intrl0.stat, + GENET_INTRL_0, MDIO_DONE, 1); + break; case BCM2838_GENET_TDMA_REGS ... BCM2838_GENET_TDMA_REGS + sizeof(BCM2838GenetRegsTdma) - 1: - qemu_log_mask(LOG_UNIMP, - "UMAC MDIO and TDMA aren't implemented yet"); + qemu_log_mask(LOG_UNIMP, "TDMA isn't implemented yet"); break; default: break; @@ -452,6 +573,7 @@ static void bcm2838_genet_reset(DeviceState *d) =20 trace_bcm2838_genet_reset("done"); =20 + bcm2838_genet_set_qemu_mac(s); bcm2838_genet_phy_reset(s); } =20 diff --git a/include/hw/net/bcm2838_genet.h b/include/hw/net/bcm2838_genet.h index b9d6d35cce..7a483bd265 100644 --- a/include/hw/net/bcm2838_genet.h +++ b/include/hw/net/bcm2838_genet.h @@ -101,7 +101,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(BCM2838GenetState, BCM2838_G= ENET) #define BCM2838_GENET_EXP_DATA BCM2838_GENET_PHY_REG(exp_data) #define BCM2838_GENET_EXP_SEL BCM2838_GENET_PHY_REG(exp_ctrl) =20 -#define BCM2838_GENET_PHY_AUX_CTL_MISC 0x7 +#define BCM2838_GENET_PHY_AUX_CTL_AUXCTL 0x0 +#define BCM2838_GENET_PHY_AUX_CTL_MISC 0x7 #define BCM2838_GENET_PHY_AUX_CTL_REGS_SIZE 8 =20 #define BCM2838_GENET_PHY_EXP_SHD_BLOCKS_CNT 256 --=20 2.34.1