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Sun, 18 Feb 2024 17:18:03 -0800 (PST) From: Sergey Kambalin X-Google-Original-From: Sergey Kambalin To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Sergey Kambalin Subject: [PATCH v5 13/41] Add BCM2838 PCIE Root Complex Date: Sun, 18 Feb 2024 19:17:11 -0600 Message-Id: <20240219011739.2316619-14-sergey.kambalin@auriga.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219011739.2316619-1-sergey.kambalin@auriga.com> References: <20240219011739.2316619-1-sergey.kambalin@auriga.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::112c; envelope-from=serg.oker@gmail.com; helo=mail-yw1-x112c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1708305983959100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Sergey Kambalin --- hw/arm/bcm2838_pcie.c | 82 +++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 5 ++- include/hw/arm/bcm2838_pcie.h | 53 ++++++++++++++++++++++ 3 files changed, 139 insertions(+), 1 deletion(-) create mode 100644 hw/arm/bcm2838_pcie.c create mode 100644 include/hw/arm/bcm2838_pcie.h diff --git a/hw/arm/bcm2838_pcie.c b/hw/arm/bcm2838_pcie.c new file mode 100644 index 0000000000..cb1370433e --- /dev/null +++ b/hw/arm/bcm2838_pcie.c @@ -0,0 +1,82 @@ +/* + * BCM2838 PCIe Root Complex emulation + * + * Copyright (C) 2022 Ovchinnikov Vitalii + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/irq.h" +#include "hw/pci-host/gpex.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "qemu/module.h" +#include "hw/arm/bcm2838_pcie.h" +#include "trace.h" + +/* + * RC root part (D0:F0) + */ + +static void bcm2838_pcie_root_port_reset_hold(Object *obj) +{ + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(obj); + PCIDevice *dev =3D PCI_DEVICE(obj); + BCM2838PcieRootState *s =3D BCM2838_PCIE_ROOT(dev); + + if (rpc->parent_phases.hold) { + rpc->parent_phases.hold(obj); + } + + memset(s->regs, 0xFF, sizeof(s->regs)); +} + +static void bcm2838_pcie_root_init(Object *obj) +{ + PCIBridge *br =3D PCI_BRIDGE(obj); + br->bus_name =3D "pcie.1"; +} + +static void bcm2838_pcie_root_class_init(ObjectClass *class, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(class); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(class); + ResettableClass *rc =3D RESETTABLE_CLASS(class); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_CLASS(class); + + dc->desc =3D "BCM2711 PCIe Bridge"; + /* + * PCI-facing part of the host bridge, not usable without the host-fac= ing + * part, which can't be device_add'ed. + */ + + resettable_class_set_parent_phases(rc, NULL, + bcm2838_pcie_root_port_reset_hold, + NULL, &rpc->parent_phases); + + dc->user_creatable =3D false; + k->vendor_id =3D BCM2838_PCIE_VENDOR_ID; + k->device_id =3D BCM2838_PCIE_DEVICE_ID; + k->revision =3D BCM2838_PCIE_REVISION; + + rpc->exp_offset =3D BCM2838_PCIE_EXP_CAP_OFFSET; + rpc->aer_offset =3D BCM2838_PCIE_AER_CAP_OFFSET; +} + +static const TypeInfo bcm2838_pcie_root_info =3D { + .name =3D TYPE_BCM2838_PCIE_ROOT, + .parent =3D TYPE_PCIE_ROOT_PORT, + .instance_size =3D sizeof(BCM2838PcieRootState), + .instance_init =3D bcm2838_pcie_root_init, + .class_init =3D bcm2838_pcie_root_class_init, +}; + +static void bcm2838_pcie_register(void) +{ + type_register_static(&bcm2838_pcie_root_info); +} + +type_init(bcm2838_pcie_register) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 6808135c1f..39f6df7431 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -30,7 +30,10 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files(= 'allwinner-a10.c', 'cubi arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', '= orangepi.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c',= 'bananapi_m2u.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) -arm_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm28= 38.c', 'raspi4b.c')) +arm_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files( + 'bcm2838.c', + 'bcm2838_pcie.c', + 'raspi4b.c')) arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) diff --git a/include/hw/arm/bcm2838_pcie.h b/include/hw/arm/bcm2838_pcie.h new file mode 100644 index 0000000000..39828f817f --- /dev/null +++ b/include/hw/arm/bcm2838_pcie.h @@ -0,0 +1,53 @@ +/* + * BCM2838 PCIe Root Complex emulation + * + * Copyright (C) 2022 Ovchinnikov Vitalii + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef BCM2838_PCIE_H +#define BCM2838_PCIE_H + +#include "exec/hwaddr.h" +#include "hw/sysbus.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie_host.h" +#include "hw/pci/pcie_port.h" +#include "qom/object.h" + +#define TYPE_BCM2838_PCIE_ROOT "bcm2838-pcie-root" +OBJECT_DECLARE_TYPE(BCM2838PcieRootState, BCM2838PcieRootClass, + BCM2838_PCIE_ROOT) + +#define BCM2838_PCIE_VENDOR_ID 0x14E4 +#define BCM2838_PCIE_DEVICE_ID 0x2711 +#define BCM2838_PCIE_REVISION 20 + +#define BCM2838_PCIE_REGS_SIZE 0x9310 +#define BCM2838_PCIE_NUM_IRQS 4 + +#define BCM2838_PCIE_EXP_CAP_OFFSET 0xAC +#define BCM2838_PCIE_AER_CAP_OFFSET 0x100 + +#define BCM2838_PCIE_EXT_CFG_DATA 0x8000 +#define BCM2838_PCIE_EXT_CFG_INDEX 0x9000 + +struct BCM2838PcieRootState { + /*< private >*/ + PCIESlot parent_obj; + + /*< public >*/ + uint8_t regs[BCM2838_PCIE_REGS_SIZE - PCIE_CONFIG_SPACE_SIZE]; +}; + +struct BCM2838PcieRootClass { + /*< private >*/ + PCIERootPortClass parent_obj; + + /*< public >*/ + void (*parent_realize)(PCIDevice *dev, Error **errp); +}; + + +#endif /* BCM2838_PCIE_H */ --=20 2.34.1