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Fri, 16 Feb 2024 17:58:16 -0800 (PST) From: Guenter Roeck To: qemu-devel@nongnu.org Cc: Guenter Roeck , Richard Henderson , Charlie Jenkins , Helge Deller Subject: [PATCH v2] target: hppa: Fix unaligned double word accesses for hppa64 Date: Fri, 16 Feb 2024 17:58:11 -0800 Message-Id: <20240217015811.1975411-1-linux@roeck-us.net> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=groeck7@gmail.com; helo=mail-ot1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1708135156701100001 Content-Type: text/plain; charset="utf-8" Unaligned 64-bit accesses were found in Linux to clobber carry bits, resulting in bad results if an arithmetic operation involving a carry bit was executed after an unaligned 64-bit operation. hppa 2.0 defines additional carry bits in PSW register bits 32..39. When restoring PSW after executing an unaligned instruction trap, those bits were not cleared and ended up to be active all the time. Since there are no bits other than the upper carry bits needed in the upper 32 bit of env->psw and since those are stored in env->psw_cb, just clear the entire upper 32 bit when storing psw to solve the problem unconditionally. Fixes: 931adff31478 ("target/hppa: Update cpu_hppa_get/put_psw for hppa64") Cc: Richard Henderson Cc: Charlie Jenkins Cc: Helge Deller Reviewed-by: Richard Henderson Signed-off-by: Guenter Roeck --- v2: Rework to not require conditional code [Richard] Add Richard's Reviewed-by: tag target/hppa/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 859644c47a..9d217d051c 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -76,7 +76,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) } psw &=3D ~reserved; =20 - env->psw =3D psw & ~(PSW_N | PSW_V | PSW_CB); + env->psw =3D psw & (uint32_t)~(PSW_N | PSW_V | PSW_CB); + env->psw_n =3D (psw / PSW_N) & 1; env->psw_v =3D -((psw / PSW_V) & 1); =20 --=20 2.39.2