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Fri, 16 Feb 2024 16:01:48 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH RFC 3/8] target/riscv: Enable S*stateen bits for AIA Date: Fri, 16 Feb 2024 16:01:29 -0800 Message-Id: <20240217000134.3634191-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217000134.3634191-1-atishp@rivosinc.com> References: <20240217000134.3634191-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708128232756100001 Content-Type: text/plain; charset="utf-8" As per the ratified AIA spec v1.0, three stateen bits control AIA CSR access. Bit 60 controls the indirect CSRs Bit 59 controls the most AIA CSR state Bit 58 controls the IMSIC state such as stopei and vstopei Enable the corresponding bits in [m|h]stateen and enable corresponding checks in the CSR accessor functions. Signed-off-by: Atish Patra --- target/riscv/csr.c | 89 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1af0c8890a2b..89a1325a02a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -316,19 +316,42 @@ static int smode32(CPURISCVState *env, int csrno) =20 static int aia_smode(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 + if (csrno =3D=3D CSR_STOPEI) { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); + } else { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return smode(env, csrno); } =20 static int aia_smode32(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return smode32(env, csrno); } =20 @@ -552,15 +575,38 @@ static RISCVException pointer_masking(CPURISCVState *= env, int csrno) =20 static int aia_hmode(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 - return hmode(env, csrno); + if (csrno =3D=3D CSR_VSTOPEI) { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); + } else { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + return hmode(env, csrno); } =20 static int aia_hmode32(CPURISCVState *env, int csrno) { + int ret; + + if (!riscv_cpu_cfg(env)->ext_ssaia) { + return RISCV_EXCP_ILLEGAL_INST; + } + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } @@ -1851,6 +1897,12 @@ static int rmw_xiselect(CPURISCVState *env, int csrn= o, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { target_ulong *iselect; + int ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 /* Translate CSR number for VS-mode */ csrno =3D sxcsrind_xlate_vs_csrno(env, csrno); @@ -2020,6 +2072,11 @@ static int rmw_xireg(CPURISCVState *env, int csrno, = target_ulong *val, int ret =3D -EINVAL; target_ulong isel; =20 + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + /* Translate CSR number for VS-mode */ csrno =3D sxcsrind_xlate_vs_csrno(env, csrno); =20 @@ -2419,6 +2476,23 @@ static RISCVException write_mstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D SMSTATEEN0_FCSR; } =20 + /* + * TODO: Do we need to check ssaia as well ? Can we enable ssaia witho= ut + * smaia ? + */ + if (riscv_cpu_cfg(env)->ext_smaia) { + wr_mask |=3D SMSTATEEN0_SVSLCT; + } + + /* + * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMS= IC is + * implemented. However, that information is with MachineState and we = can't + * figure that out in csr.c. Just enable if Smaia is available. + */ + if (riscv_cpu_cfg(env)->ext_smaia) { + wr_mask |=3D (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); + } + return write_mstateen(env, csrno, wr_mask, new_val); } =20 @@ -2495,6 +2569,19 @@ static RISCVException write_hstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D SMSTATEEN0_FCSR; } =20 + if (riscv_cpu_cfg(env)->ext_ssaia) { + wr_mask |=3D SMSTATEEN0_SVSLCT; + } + + /* + * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMS= IC is + * implemented. However, that information is with MachineState and we = can't + * figure that out in csr.c. Just enable if Ssaia is available. + */ + if (riscv_cpu_cfg(env)->ext_ssaia) { + wr_mask |=3D (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); + } + return write_hstateen(env, csrno, wr_mask, new_val); } =20 --=20 2.34.1