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Fri, 16 Feb 2024 16:01:45 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH RFC 1/8] target/riscv: Add properties for Indirect CSR Access extension Date: Fri, 16 Feb 2024 16:01:27 -0800 Message-Id: <20240217000134.3634191-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217000134.3634191-1-atishp@rivosinc.com> References: <20240217000134.3634191-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708128148670100005 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8af99ed2f6de..ff7c6c7c380e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -152,10 +152,12 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1348,6 +1350,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), + MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false), + MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index eabbecb8f962..b9086464752e 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -74,6 +74,8 @@ struct RISCVCPUConfig { bool ext_smstateen; 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Fri, 16 Feb 2024 16:01:47 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH RFC 2/8] target/riscv: Decouple AIA processing from xiselect and xireg Date: Fri, 16 Feb 2024 16:01:28 -0800 Message-Id: <20240217000134.3634191-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217000134.3634191-1-atishp@rivosinc.com> References: <20240217000134.3634191-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708128182554100005 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/csr.c | 147 +++++++++++++++++++++++++++++++++++++-------- 1 file changed, 122 insertions(+), 25 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8829dee7bc75..1af0c8890a2b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -287,6 +287,15 @@ static int aia_any32(CPURISCVState *env, int csrno) return any32(env, csrno); } =20 +static int sxcsrind_or_aia_any(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrin= d) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + static RISCVException smode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS)) { @@ -323,6 +332,15 @@ static int aia_smode32(CPURISCVState *env, int csrno) return smode32(env, csrno); } =20 +static int sxcsrind_or_aia_smode(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_ssaia && !riscv_cpu_cfg(env)->ext_sscsrin= d) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + static RISCVException hmode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVH)) { @@ -342,6 +360,15 @@ static RISCVException hmode32(CPURISCVState *env, int = csrno) =20 } =20 +static int sxcsrind_or_aia_hmode(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_ssaia && !riscv_cpu_cfg(env)->ext_sscsrin= d) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static RISCVException umode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVU)) { @@ -1804,13 +1831,29 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, i= nt csrno) }; } =20 +static int sxcsrind_xlate_vs_csrno(CPURISCVState *env, int csrno) +{ + if (!env->virt_enabled) { + return csrno; + } + + switch (csrno) { + case CSR_SISELECT: + return CSR_VSISELECT; + case CSR_SIREG: + return CSR_VSIREG; + default: + return csrno; + }; +} + static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { target_ulong *iselect; =20 /* Translate CSR number for VS-mode */ - csrno =3D aia_xlate_vs_csrno(env, csrno); + csrno =3D sxcsrind_xlate_vs_csrno(env, csrno); =20 /* Find the iselect CSR based on CSR number */ switch (csrno) { @@ -1839,6 +1882,12 @@ static int rmw_xiselect(CPURISCVState *env, int csrn= o, target_ulong *val, return RISCV_EXCP_NONE; } =20 +static bool xiselect_aia_range(target_ulong isel) +{ + return (ISELECT_IPRIO0 <=3D isel && isel <=3D ISELECT_IPRIO15) || + (ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LAST); +} + static int rmw_iprio(target_ulong xlen, target_ulong iselect, uint8_t *iprio, target_ulong *val, target_ulong new_val, @@ -1884,44 +1933,44 @@ static int rmw_iprio(target_ulong xlen, return 0; } =20 -static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, - target_ulong new_val, target_ulong wr_mask) +static int rmw_xireg_aia(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) { - bool virt, isel_reserved; - uint8_t *iprio; + bool virt =3D false, isel_reserved =3D false; int ret =3D -EINVAL; - target_ulong priv, isel, vgein; - - /* Translate CSR number for VS-mode */ - csrno =3D aia_xlate_vs_csrno(env, csrno); + uint8_t *iprio; + target_ulong priv, vgein; =20 - /* Decode register details from CSR number */ - virt =3D false; - isel_reserved =3D false; + /* VS-mode CSR number passed in has already been translated */ switch (csrno) { case CSR_MIREG: + if (!riscv_cpu_cfg(env)->ext_smaia) { + goto done; + } iprio =3D env->miprio; - isel =3D env->miselect; priv =3D PRV_M; break; case CSR_SIREG: - if (env->priv =3D=3D PRV_S && env->mvien & MIP_SEIP && + if (!riscv_cpu_cfg(env)->ext_ssaia || + (env->priv =3D=3D PRV_S && env->mvien & MIP_SEIP && env->siselect >=3D ISELECT_IMSIC_EIDELIVERY && - env->siselect <=3D ISELECT_IMSIC_EIE63) { + env->siselect <=3D ISELECT_IMSIC_EIE63)) { goto done; } iprio =3D env->siprio; - isel =3D env->siselect; priv =3D PRV_S; break; case CSR_VSIREG: + if (!riscv_cpu_cfg(env)->ext_ssaia) { + goto done; + } iprio =3D env->hviprio; - isel =3D env->vsiselect; priv =3D PRV_S; virt =3D true; break; default: - goto done; + goto done; }; =20 /* Find the selected guest interrupt file */ @@ -1952,10 +2001,53 @@ static int rmw_xireg(CPURISCVState *env, int csrno,= target_ulong *val, } =20 done: + /* + * If AIA is not enabled, illegal instruction exception is always + * returned regardless of whether we are in VS-mode or not + */ if (ret) { return (env->virt_enabled && virt && !isel_reserved) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } + + return RISCV_EXCP_NONE; +} + +static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + bool virt =3D false; + int ret =3D -EINVAL; + target_ulong isel; + + /* Translate CSR number for VS-mode */ + csrno =3D sxcsrind_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + switch (csrno) { + case CSR_MIREG: + isel =3D env->miselect; + break; + case CSR_SIREG: + isel =3D env->siselect; + break; + case CSR_VSIREG: + isel =3D env->vsiselect; + virt =3D true; + break; + default: + goto done; + }; + + if (xiselect_aia_range(isel)) { + return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); + } + +done: + if (ret) { + return (env->virt_enabled && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } return RISCV_EXCP_NONE; } =20 @@ -4682,8 +4774,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ - [CSR_MISELECT] =3D { "miselect", aia_any, NULL, NULL, rmw_xiselec= t }, - [CSR_MIREG] =3D { "mireg", aia_any, NULL, NULL, rmw_xireg }, + [CSR_MISELECT] =3D { "miselect", sxcsrind_or_aia_any, NULL, NULL, + rmw_xiselect }, + [CSR_MIREG] =3D { "mireg", sxcsrind_or_aia_any, NULL, NULL, + rmw_xireg }, =20 /* Machine-Level Interrupts (AIA) */ [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, @@ -4801,8 +4895,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SATP] =3D { "satp", satp, read_satp, write_satp }, =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ - [CSR_SISELECT] =3D { "siselect", aia_smode, NULL, NULL, rmw_xisele= ct }, - [CSR_SIREG] =3D { "sireg", aia_smode, NULL, NULL, rmw_xireg = }, + [CSR_SISELECT] =3D { "siselect", sxcsrind_or_aia_smode, NULL, NULL, + rmw_xiselect = }, + [CSR_SIREG] =3D { "sireg", sxcsrind_or_aia_smode, NULL, NULL, + rmw_xireg = }, =20 /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPEI] =3D { "stopei", aia_smode, NULL, NULL, rmw_xtopei= }, @@ -4881,9 +4977,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* * VS-Level Window to Indirectly Accessed Registers (H-extension with = AIA) */ - [CSR_VSISELECT] =3D { "vsiselect", aia_hmode, NULL, NULL, - rmw_xiselect = }, - [CSR_VSIREG] =3D { "vsireg", aia_hmode, NULL, NULL, rmw_xire= g }, + [CSR_VSISELECT] =3D { "vsiselect", sxcsrind_or_aia_hmode, NULL, NU= LL, + rmw_xiselect = }, + [CSR_VSIREG] =3D { "vsireg", sxcsrind_or_aia_hmode, NULL, NU= LL, + rmw_xireg = }, =20 /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPEI] =3D { "vstopei", aia_hmode, NULL, NULL, rmw_xtop= ei }, --=20 2.34.1 From nobody Fri Nov 1 05:28:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 16 Feb 2024 16:01:48 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH RFC 3/8] target/riscv: Enable S*stateen bits for AIA Date: Fri, 16 Feb 2024 16:01:29 -0800 Message-Id: <20240217000134.3634191-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217000134.3634191-1-atishp@rivosinc.com> References: <20240217000134.3634191-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708128232756100001 Content-Type: text/plain; charset="utf-8" As per the ratified AIA spec v1.0, three stateen bits control AIA CSR access. Bit 60 controls the indirect CSRs Bit 59 controls the most AIA CSR state Bit 58 controls the IMSIC state such as stopei and vstopei Enable the corresponding bits in [m|h]stateen and enable corresponding checks in the CSR accessor functions. Signed-off-by: Atish Patra --- target/riscv/csr.c | 89 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1af0c8890a2b..89a1325a02a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -316,19 +316,42 @@ static int smode32(CPURISCVState *env, int csrno) =20 static int aia_smode(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 + if (csrno =3D=3D CSR_STOPEI) { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); + } else { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return smode(env, csrno); } =20 static int aia_smode32(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return smode32(env, csrno); } =20 @@ -552,15 +575,38 @@ static RISCVException pointer_masking(CPURISCVState *= env, int csrno) =20 static int aia_hmode(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 - return hmode(env, csrno); + if (csrno =3D=3D CSR_VSTOPEI) { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); + } else { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + return hmode(env, csrno); } =20 static int aia_hmode32(CPURISCVState *env, int csrno) { + int ret; + + if (!riscv_cpu_cfg(env)->ext_ssaia) { + return RISCV_EXCP_ILLEGAL_INST; + } + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } @@ -1851,6 +1897,12 @@ static int rmw_xiselect(CPURISCVState *env, int csrn= o, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { target_ulong *iselect; + int ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 /* Translate CSR number for VS-mode */ csrno =3D sxcsrind_xlate_vs_csrno(env, csrno); @@ -2020,6 +2072,11 @@ static int rmw_xireg(CPURISCVState *env, int csrno, = target_ulong *val, int ret =3D -EINVAL; target_ulong isel; =20 + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + /* Translate CSR number for VS-mode */ csrno =3D sxcsrind_xlate_vs_csrno(env, csrno); =20 @@ -2419,6 +2476,23 @@ static RISCVException write_mstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D SMSTATEEN0_FCSR; } =20 + /* + * TODO: Do we need to check ssaia as well ? Can we enable ssaia witho= ut + * smaia ? + */ + if (riscv_cpu_cfg(env)->ext_smaia) { + wr_mask |=3D SMSTATEEN0_SVSLCT; + } + + /* + * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMS= IC is + * implemented. However, that information is with MachineState and we = can't + * figure that out in csr.c. Just enable if Smaia is available. + */ + if (riscv_cpu_cfg(env)->ext_smaia) { + wr_mask |=3D (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); + } + return write_mstateen(env, csrno, wr_mask, new_val); } =20 @@ -2495,6 +2569,19 @@ static RISCVException write_hstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D SMSTATEEN0_FCSR; } =20 + if (riscv_cpu_cfg(env)->ext_ssaia) { + wr_mask |=3D SMSTATEEN0_SVSLCT; + } + + /* + * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMS= IC is + * implemented. However, that information is with MachineState and we = can't + * figure that out in csr.c. Just enable if Ssaia is available. + */ + if (riscv_cpu_cfg(env)->ext_ssaia) { + wr_mask |=3D (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); + } + return write_hstateen(env, csrno, wr_mask, new_val); } =20 --=20 2.34.1 From nobody Fri Nov 1 05:28:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708128214; cv=none; d=zohomail.com; s=zohoarc; b=TqSLumHfJSQ4RXg9QviXgumKk35nvGaAdq9mWluszy6/MDVnKIE8EgO71N0Azw8cxO3ij+whF/0lc+SUWX6fp37fjCTYxSm8LWhqCJd/6wXeM+C0HdpxOU4Q/qwVimpJRw6S/yKLvzoER9Ry1cMLEizIJ75jsGlXL1RhI7SX0+M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708128214; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 16 Feb 2024 16:01:50 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH RFC 4/8] target/riscv: Support generic CSR indirect access Date: Fri, 16 Feb 2024 16:01:30 -0800 Message-Id: <20240217000134.3634191-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217000134.3634191-1-atishp@rivosinc.com> References: <20240217000134.3634191-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708128216800100005 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue This adds the indirect access registers required by sscsrind/smcsrind and the operations on them. Note that xiselect and xireg are used for both AIA and sxcsrind, and the behavior of accessing them depends on whether each extension is enabled and the value stored in xiselect. Co-developed-by: Atish Patra Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu_bits.h | 28 +++++++- target/riscv/csr.c | 146 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 169 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 0ee91e502e8f..3a66f83009b5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -176,6 +176,13 @@ #define CSR_MISELECT 0x350 #define CSR_MIREG 0x351 =20 +/* Machine Indirect Register Alias */ +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 + /* Machine-Level Interrupts (AIA) */ #define CSR_MTOPEI 0x35c #define CSR_MTOPI 0xfb0 @@ -225,6 +232,13 @@ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 =20 +/* Supervisor Indirect Register Alias */ +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 + /* Supervisor-Level Interrupts (AIA) */ #define CSR_STOPEI 0x15c #define CSR_STOPI 0xdb0 @@ -291,6 +305,13 @@ #define CSR_VSISELECT 0x250 #define CSR_VSIREG 0x251 =20 +/* Virtual Supervisor Indirect Alias */ +#define CSR_VSIREG2 0x252 +#define CSR_VSIREG3 0x253 +#define CSR_VSIREG4 0x255 +#define CSR_VSIREG5 0x256 +#define CSR_VSIREG6 0x257 + /* VS-Level Interrupts (H-extension with AIA) */ #define CSR_VSTOPEI 0x25c #define CSR_VSTOPI 0xeb0 @@ -847,10 +868,13 @@ typedef enum RISCVException { #define ISELECT_IMSIC_EIE63 0xff #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 -#define ISELECT_MASK 0x1ff +#define ISELECT_MASK_AIA 0x1ff + +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ +#define ISELECT_MASK_SXCSRIND 0xfff =20 /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ -#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) +#define ISELECT_IMSIC_TOPEI (ISELECT_MASK_AIA + 1) =20 /* IMSIC bits (AIA) */ #define IMSIC_TOPEI_IID_SHIFT 16 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 89a1325a02a5..a1c10f1d010a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -287,6 +287,17 @@ static int aia_any32(CPURISCVState *env, int csrno) return any32(env, csrno); } =20 +static RISCVException sxcsrind_any(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_smcsrind) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + static int sxcsrind_or_aia_any(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrin= d) { @@ -355,6 +366,17 @@ static int aia_smode32(CPURISCVState *env, int csrno) return smode32(env, csrno); } =20 +static RISCVException sxcsrind_smode(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_sscsrind) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + static int sxcsrind_or_aia_smode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia && !riscv_cpu_cfg(env)->ext_sscsrin= d) { @@ -383,6 +405,17 @@ static RISCVException hmode32(CPURISCVState *env, int = csrno) =20 } =20 +static RISCVException sxcsrind_hmode(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_sscsrind) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static int sxcsrind_or_aia_hmode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia && !riscv_cpu_cfg(env)->ext_sscsrin= d) { @@ -1926,7 +1959,12 @@ static int rmw_xiselect(CPURISCVState *env, int csrn= o, target_ulong *val, *val =3D *iselect; } =20 - wr_mask &=3D ISELECT_MASK; + if (riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsri= nd) { + wr_mask &=3D ISELECT_MASK_SXCSRIND; + } else { + wr_mask &=3D ISELECT_MASK_AIA; + } + if (wr_mask) { *iselect =3D (*iselect & ~wr_mask) | (new_val & wr_mask); } @@ -2065,6 +2103,59 @@ done: return RISCV_EXCP_NONE; } =20 +/* + * rmw_xireg_sxcsrind: Perform indirect access to xireg and xireg2-xireg6 + * + * Perform indirect access to xireg and xireg2-xireg6. + * This is a generic interface for all xireg CSRs. Apart from AIA, all oth= er + * extension using sxcsrind should be implemented here. + */ +static int rmw_xireg_sxcsrind(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + return -EINVAL; +} + +static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + bool virt =3D false; + int ret =3D -EINVAL; + target_ulong isel; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + /* Translate CSR number for VS-mode */ + csrno =3D sxcsrind_xlate_vs_csrno(env, csrno); + + if (CSR_MIREG <=3D csrno && csrno <=3D CSR_MIREG6 && + csrno !=3D CSR_MIREG4 - 1) { + isel =3D env->miselect; + } else if (CSR_SIREG <=3D csrno && csrno <=3D CSR_SIREG6 && + csrno !=3D CSR_SIREG4 - 1) { + isel =3D env->siselect; + } else if (CSR_VSIREG <=3D csrno && csrno <=3D CSR_VSIREG6 && + csrno !=3D CSR_VSIREG4 - 1) { + isel =3D env->vsiselect; + virt =3D true; + } else { + goto done; + } + + return rmw_xireg_sxcsrind(env, csrno, isel, val, new_val, wr_mask); + +done: + if (ret) { + return (env->virt_enabled && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { @@ -2096,8 +2187,21 @@ static int rmw_xireg(CPURISCVState *env, int csrno, = target_ulong *val, goto done; }; =20 + /* + * Use the xiselect range to determine actual op on xireg. + * + * Since we only checked the existence of AIA or Indirect Access in the + * predicate, we should check the existence of the exact extension when + * we get to a specific range and return illegal instruction exception= even + * in VS-mode. + */ if (xiselect_aia_range(isel)) { return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); + } else if (riscv_cpu_cfg(env)->ext_smcsrind || + riscv_cpu_cfg(env)->ext_sscsrind) { + return rmw_xireg_sxcsrind(env, csrno, isel, val, new_val, wr_mask); + } else { + return RISCV_EXCP_ILLEGAL_INST; } =20 done: @@ -2480,7 +2584,7 @@ static RISCVException write_mstateen0(CPURISCVState *= env, int csrno, * TODO: Do we need to check ssaia as well ? Can we enable ssaia witho= ut * smaia ? */ - if (riscv_cpu_cfg(env)->ext_smaia) { + if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind)= { wr_mask |=3D SMSTATEEN0_SVSLCT; } =20 @@ -2569,7 +2673,7 @@ static RISCVException write_hstateen0(CPURISCVState *= env, int csrno, wr_mask |=3D SMSTATEEN0_FCSR; } =20 - if (riscv_cpu_cfg(env)->ext_ssaia) { + if (riscv_cpu_cfg(env)->ext_ssaia || riscv_cpu_cfg(env)->ext_sscsrind)= { wr_mask |=3D SMSTATEEN0_SVSLCT; } =20 @@ -4866,6 +4970,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIREG] =3D { "mireg", sxcsrind_or_aia_any, NULL, NULL, rmw_xireg }, =20 + /* Machine Indirect Register Alias */ + [CSR_MIREG2] =3D { "mireg2", sxcsrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MIREG3] =3D { "mireg3", sxcsrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MIREG4] =3D { "mireg4", sxcsrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MIREG5] =3D { "mireg5", sxcsrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MIREG6] =3D { "mireg6", sxcsrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + /* Machine-Level Interrupts (AIA) */ [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, @@ -4987,6 +5103,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SIREG] =3D { "sireg", sxcsrind_or_aia_smode, NULL, NULL, rmw_xireg = }, =20 + /* Supervisor Indirect Register Alias */ + [CSR_SIREG2] =3D { "sireg2", sxcsrind_smode, NULL, NULL, rmw_xire= gi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_SIREG3] =3D { "sireg3", sxcsrind_smode, NULL, NULL, rmw_xire= gi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_SIREG4] =3D { "sireg4", sxcsrind_smode, NULL, NULL, rmw_xire= gi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_SIREG5] =3D { "sireg5", sxcsrind_smode, NULL, NULL, rmw_xire= gi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_SIREG6] =3D { "sireg6", sxcsrind_smode, NULL, NULL, rmw_xire= gi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPEI] =3D { "stopei", aia_smode, NULL, NULL, rmw_xtopei= }, [CSR_STOPI] =3D { "stopi", aia_smode, read_stopi }, @@ -5069,6 +5197,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VSIREG] =3D { "vsireg", sxcsrind_or_aia_hmode, NULL, NU= LL, rmw_xireg = }, =20 + /* Virtual Supervisor Indirect Alias */ + [CSR_VSIREG2] =3D { "vsireg2", sxcsrind_hmode, NULL, NULL, rmw_xir= egi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSIREG3] =3D { "vsireg3", sxcsrind_hmode, NULL, NULL, rmw_xir= egi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSIREG4] =3D { "vsireg4", sxcsrind_hmode, NULL, NULL, rmw_xir= egi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSIREG5] =3D { "vsireg5", sxcsrind_hmode, NULL, NULL, rmw_xir= egi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSIREG6] =3D { "vsireg6", sxcsrind_hmode, NULL, NULL, rmw_xir= egi, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPEI] =3D { "vstopei", aia_hmode, NULL, NULL, rmw_xtop= ei }, [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, --=20 2.34.1 From nobody Fri Nov 1 05:28:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 16 Feb 2024 16:01:51 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH RFC 5/8] target/riscv: Add smcdeleg/ssccfg properties Date: Fri, 16 Feb 2024 16:01:31 -0800 Message-Id: <20240217000134.3634191-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217000134.3634191-1-atishp@rivosinc.com> References: <20240217000134.3634191-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708128232758100002 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue This adds the properties of smcdeleg/ssccfg. Implementation will be in future patches. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ff7c6c7c380e..c5ec203fb8fd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -151,11 +151,13 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_12_0, ext_smcdeleg), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_12_0, ext_ssccfg), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), @@ -1352,6 +1354,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false), MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), + MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false), + MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index b9086464752e..a3be34c88ef0 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -76,6 +76,8 @@ struct RISCVCPUConfig { bool ext_smcntrpmf; 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charset="utf-8" From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 8 +++++++- target/riscv/machine.c | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 85afde48fade..d7dcfdb0e5e0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -342,6 +342,7 @@ struct CPUArchState { target_ulong scounteren; target_ulong mcounteren; =20 + target_ulong scountinhibit; target_ulong mcountinhibit; =20 /* PMU cycle & instret privilege mode filtering */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3a66f83009b5..0bffec3476ab 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -213,6 +213,9 @@ #define CSR_SSTATEEN2 0x10E #define CSR_SSTATEEN3 0x10F =20 +/* Supervisor Counter Delegation */ +#define CSR_SCOUNTINHIBIT 0x120 + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -779,6 +782,7 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_CDE (1ULL << 60) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -870,7 +874,9 @@ typedef enum RISCVException { #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 #define ISELECT_MASK_AIA 0x1ff =20 -/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ +/* [M|S|VS]SELCT value for Indirect CSR Access Extension */ +#define ISELECT_CD_FIRST 0x40 +#define ISELECT_CD_LAST 0x5f #define ISELECT_MASK_SXCSRIND 0xfff =20 /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 72fe2374dc2a..d26742f99ed7 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -400,6 +400,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.siselect, RISCVCPU), VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.scountinhibit, RISCVCPU), VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, vmstate_pmu_ctr_state, PMUCTRState), --=20 2.34.1 From nobody Fri Nov 1 05:28:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 16 Feb 2024 16:01:54 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH RFC 7/8] target/riscv: Add select value range check for counter delegation Date: Fri, 16 Feb 2024 16:01:33 -0800 Message-Id: <20240217000134.3634191-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217000134.3634191-1-atishp@rivosinc.com> References: <20240217000134.3634191-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708128232765100003 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv/csr.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a1c10f1d010a..d5218a47ffbf 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1978,6 +1978,11 @@ static bool xiselect_aia_range(target_ulong isel) (ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LAST); } =20 +static bool xiselect_cd_range(target_ulong isel) +{ + return (ISELECT_CD_FIRST <=3D isel && isel <=3D ISELECT_CD_LAST); +} + static int rmw_iprio(target_ulong xlen, target_ulong iselect, uint8_t *iprio, target_ulong *val, target_ulong new_val, @@ -2103,6 +2108,17 @@ done: return RISCV_EXCP_NONE; } =20 +static int rmw_xireg_cd(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + if (!riscv_cpu_cfg(env)->ext_smcdeleg) { + return RISCV_EXCP_ILLEGAL_INST; + } + /* TODO: Implement the functionality later */ + return RISCV_EXCP_NONE; +} + /* * rmw_xireg_sxcsrind: Perform indirect access to xireg and xireg2-xireg6 * @@ -2114,7 +2130,25 @@ static int rmw_xireg_sxcsrind(CPURISCVState *env, in= t csrno, target_ulong isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - return -EINVAL; + int ret =3D -EINVAL; + bool virt =3D csrno =3D=3D CSR_VSIREG ? true : false; + + if (xiselect_cd_range(isel)) { + ret =3D rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask); + } else { + /* + * As per the specification, access to unimplented region is undef= ined + * but recommendation is to raise illegal instruction exception. + */ + return RISCV_EXCP_ILLEGAL_INST; + } + + if (ret) { + return (env->virt_enabled && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; } =20 static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val, --=20 2.34.1 From nobody Fri Nov 1 05:28:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 16 Feb 2024 16:01:55 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [PATCH RFC 8/8] target/riscv: Add counter delegation/configuration support Date: Fri, 16 Feb 2024 16:01:34 -0800 Message-Id: <20240217000134.3634191-9-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217000134.3634191-1-atishp@rivosinc.com> References: <20240217000134.3634191-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d32; envelope-from=atishp@rivosinc.com; helo=mail-io1-xd32.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1708128180809100001 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/csr.c | 307 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 294 insertions(+), 13 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d5218a47ffbf..3542c522ba07 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -366,6 +366,21 @@ static int aia_smode32(CPURISCVState *env, int csrno) return smode32(env, csrno); } =20 +static RISCVException scountinhibit_pred(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssccfg || !cpu->cfg.ext_smcdeleg) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + + return smode(env, csrno); +} + static RISCVException sxcsrind_smode(CPURISCVState *env, int csrno) { RISCVCPU *cpu =3D env_archcpu(env); @@ -1089,9 +1104,9 @@ done: return result; } =20 -static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) +static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong= val, + uint32_t ctr_idx) { - int ctr_idx =3D csrno - CSR_MCYCLE; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D val; =20 @@ -1115,9 +1130,9 @@ static int write_mhpmcounter(CPURISCVState *env, int = csrno, target_ulong val) return RISCV_EXCP_NONE; } =20 -static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) +static RISCVException riscv_pmu_write_ctrh(CPURISCVState *env, target_ulon= g val, + uint32_t ctr_idx) { - int ctr_idx =3D csrno - CSR_MCYCLEH; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D counter->mhpmcounter_val; uint64_t mhpmctrh_val =3D val; @@ -1138,6 +1153,20 @@ static int write_mhpmcounterh(CPURISCVState *env, in= t csrno, target_ulong val) return RISCV_EXCP_NONE; } =20 +static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) +{ + int ctr_idx =3D csrno - CSR_MCYCLE; + + return riscv_pmu_write_ctr(env, val, ctr_idx); +} + +static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong = val) +{ + int ctr_idx =3D csrno - CSR_MCYCLEH; + + return riscv_pmu_write_ctrh(env, val, ctr_idx); +} + static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong = *val, bool upper_half, uint32_t ctr_idx) { @@ -1207,6 +1236,167 @@ static int read_hpmcounterh(CPURISCVState *env, int= csrno, target_ulong *val) return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 +static int rmw_cd_mhpmcounter(CPURISCVState *env, int ctr_idx, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + if (wr_mask !=3D 0 && wr_mask !=3D -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + riscv_pmu_read_ctr(env, val, false, ctr_idx); + } else if (wr_mask) { + riscv_pmu_write_ctr(env, new_val, ctr_idx); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + if (wr_mask !=3D 0 && wr_mask !=3D -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + riscv_pmu_read_ctr(env, val, true, ctr_idx); + } else if (wr_mask) { + riscv_pmu_write_ctrh(env, new_val, ctr_idx); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + uint64_t mhpmevt_val =3D new_val; + + if (wr_mask !=3D 0 && wr_mask !=3D -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + *val =3D env->mhpmevent_val[evt_index]; + if (riscv_cpu_cfg(env)->ext_sscofpmf) { + *val &=3D ~MHPMEVENT_BIT_MINH; + } + } else if (wr_mask) { + wr_mask &=3D ~MHPMEVENT_BIT_MINH; + mhpmevt_val =3D (new_val & wr_mask) | + (env->mhpmevent_val[evt_index] & ~wr_mask); + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmevt_val =3D mhpmevt_val | + ((uint64_t)env->mhpmeventh_val[evt_index] << 32); + } + env->mhpmevent_val[evt_index] =3D mhpmevt_val; + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmeventh(CPURISCVState *env, int evt_index, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + uint64_t mhpmevth_val; + uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + + if (wr_mask !=3D 0 && wr_mask !=3D -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + *val =3D env->mhpmeventh_val[evt_index]; + if (riscv_cpu_cfg(env)->ext_sscofpmf) { + *val &=3D ~MHPMEVENTH_BIT_MINH; + } + } else if (wr_mask) { + wr_mask &=3D ~MHPMEVENTH_BIT_MINH; + env->mhpmeventh_val[evt_index] =3D + (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_ma= sk); + mhpmevth_val =3D env->mhpmeventh_val[evt_index]; + mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong = *val, + target_ulong new_val, target_ulong wr_mask) +{ + switch (cfg_index) { + case 0: /* CYCLECFG */ + if (wr_mask) { + wr_mask &=3D ~MCYCLECFG_BIT_MINH; + env->mcyclecfg =3D (new_val & wr_mask) | (env->mcyclecfg & ~wr= _mask); + } else { + *val =3D env->mcyclecfg &=3D ~MHPMEVENTH_BIT_MINH; + } + break; + case 2: /* INSTRETCFG */ + if (wr_mask) { + wr_mask &=3D ~MINSTRETCFG_BIT_MINH; + env->minstretcfg =3D (new_val & wr_mask) | + (env->minstretcfg & ~wr_mask); + } else { + *val =3D env->minstretcfg &=3D ~MHPMEVENTH_BIT_MINH; + } + break; + default: + return -EINVAL; + } + return 0; +} + +static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong= *val, + target_ulong new_val, target_ulong wr_mask) +{ + + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + switch (cfg_index) { + case 0: /* CYCLECFGH */ + if (wr_mask) { + wr_mask &=3D ~MCYCLECFGH_BIT_MINH; + env->mcyclecfgh =3D (new_val & wr_mask) | + (env->mcyclecfgh & ~wr_mask); + } else { + *val =3D env->mcyclecfgh; + } + break; + case 2: /* INSTRETCFGH */ + if (wr_mask) { + wr_mask &=3D ~MINSTRETCFGH_BIT_MINH; + env->minstretcfgh =3D (new_val & wr_mask) | + (env->minstretcfgh & ~wr_mask); + } else { + *val =3D env->minstretcfgh; + } + break; + default: + return -EINVAL; + } + return 0; +} + + static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) { int mhpmevt_start =3D CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; @@ -1215,6 +1405,14 @@ static int read_scountovf(CPURISCVState *env, int cs= rno, target_ulong *val) target_ulong *mhpm_evt_val; uint64_t of_bit_mask; =20 + /* Virtualize scountovf for counter delegation */ + if (riscv_cpu_cfg(env)->ext_sscofpmf && + riscv_cpu_cfg(env)->ext_ssccfg && + get_field(env->menvcfg, MENVCFG_CDE) && + env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mhpm_evt_val =3D env->mhpmeventh_val; of_bit_mask =3D MHPMEVENTH_BIT_OF; @@ -2112,11 +2310,70 @@ static int rmw_xireg_cd(CPURISCVState *env, int csr= no, target_ulong isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - if (!riscv_cpu_cfg(env)->ext_smcdeleg) { + int ret =3D -EINVAL; + int ctr_index =3D isel - ISELECT_CD_FIRST; + int isel_hpm_start =3D ISELECT_CD_FIRST + 3; + + if (!riscv_cpu_cfg(env)->ext_smcdeleg || !riscv_cpu_cfg(env)->ext_sscc= fg) { return RISCV_EXCP_ILLEGAL_INST; } - /* TODO: Implement the functionality later */ - return RISCV_EXCP_NONE; + + /* Invalid siselect value for reserved */ + if (ctr_index =3D=3D 1) { + goto done; + } + + /* sireg4 and sireg5 provides access RV32 only CSRs */ + if (((csrno =3D=3D CSR_SIREG5) || (csrno =3D=3D CSR_SIREG4)) && + (riscv_cpu_mxl(env) !=3D MXL_RV32)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + /* Check Sscofpmf dependancy */ + if (!riscv_cpu_cfg(env)->ext_sscofpmf && csrno =3D=3D CSR_SIREG5 && + (isel_hpm_start <=3D isel && isel <=3D ISELECT_CD_LAST)) { + goto done; + } + + /* Check smcntrpmf dependancy */ + if (!riscv_cpu_cfg(env)->ext_smcntrpmf && + (csrno =3D=3D CSR_SIREG2 || csrno =3D=3D CSR_SIREG5) && + (ISELECT_CD_FIRST <=3D isel && isel < isel_hpm_start)) { + goto done; + } + + if (!get_field(env->mcounteren, BIT(ctr_index)) || + !get_field(env->menvcfg, MENVCFG_CDE)) { + goto done; + } + + switch (csrno) { + case CSR_SIREG: + ret =3D rmw_cd_mhpmcounter(env, ctr_index, val, new_val, wr_mask); + break; + case CSR_SIREG4: + ret =3D rmw_cd_mhpmcounterh(env, ctr_index, val, new_val, wr_mask); + break; + case CSR_SIREG2: + if (ctr_index <=3D 2) { + ret =3D rmw_cd_ctr_cfg(env, ctr_index, val, new_val, wr_mask); + } else { + ret =3D rmw_cd_mhpmevent(env, ctr_index, val, new_val, wr_mask= ); + } + break; + case CSR_SIREG5: + if (ctr_index <=3D 2) { + ret =3D rmw_cd_ctr_cfgh(env, ctr_index, val, new_val, wr_mask); + } else { + ret =3D rmw_cd_mhpmeventh(env, ctr_index, val, new_val, wr_mas= k); + } + break; + default: + goto done; + } + +done: + return ret; } =20 /* @@ -2335,14 +2592,15 @@ static RISCVException write_mcountinhibit(CPURISCVS= tate *env, int csrno, int cidx; PMUCTRState *counter; RISCVCPU *cpu =3D env_archcpu(env); + uint32_t present_ctrs =3D cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTER= EN_IR; =20 /* WARL register - disable unavailable counters; TM bit is always 0 */ - env->mcountinhibit =3D - val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR); + env->mcountinhibit =3D val & present_ctrs; =20 /* Check if any other counter is also monitoring cycles/instructions */ for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { - if (!get_field(env->mcountinhibit, BIT(cidx))) { + if ((BIT(cidx) & present_ctrs) && + (!get_field(env->mcountinhibit, BIT(cidx)))) { counter =3D &env->pmu_ctrs[cidx]; counter->started =3D true; } @@ -2351,6 +2609,21 @@ static RISCVException write_mcountinhibit(CPURISCVSt= ate *env, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_scountinhibit(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* S-mode can only access the bits delegated by M-mode */ + *val =3D env->mcountinhibit & env->mcounteren; + return RISCV_EXCP_NONE; +} + +static RISCVException write_scountinhibit(CPURISCVState *env, int csrno, + target_ulong val) +{ + write_mcountinhibit(env, csrno, val & env->mcounteren); + return RISCV_EXCP_NONE; +} + static RISCVException read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2453,12 +2726,14 @@ static RISCVException write_menvcfg(CPURISCVState *= env, int csrno, target_ulong val) { const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); - uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCF= G_CBZE; + uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | + MENVCFG_CBZE | MENVCFG_CDE; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_smcdeleg ? MENVCFG_CDE : 0); } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 @@ -2478,7 +2753,8 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_smcdeleg ? MENVCFG_CDE : 0); uint64_t valh =3D (uint64_t)val << 32; =20 env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); @@ -5102,6 +5378,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_sstateen_1_3, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 + /* Supervisor Counter Delegation */ + [CSR_SCOUNTINHIBIT] =3D {"scountinhibit", scountinhibit_pred, + read_scountinhibit, write_scountinhibit, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, --=20 2.34.1