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Fri, 16 Feb 2024 03:04:41 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [PATCH 13/21] hw/pci-host/raven: Embedded OrIRQ in PRePPCIState Date: Fri, 16 Feb 2024 12:03:04 +0100 Message-ID: <20240216110313.17039-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240216110313.17039-1-philmd@linaro.org> References: <20240216110313.17039-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philmd@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708081622758100007 Since we know the size of the OrIRQ object, we can initialize it directly in place with object_initialize_child(). Doing so we also set the QOM parent <-> child relationship. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/raven.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index c7a0a2878a..9e47caebc5 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -60,7 +60,7 @@ DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRI= DGE, struct PRePPCIState { PCIHostState parent_obj; =20 - OrIRQState *or_irq; + OrIRQState or_irq; qemu_irq pci_irqs[PCI_NUM_PINS]; PCIBus pci_bus; AddressSpace pci_io_as; @@ -249,14 +249,14 @@ static void raven_pcihost_realizefn(DeviceState *d, E= rror **errp) } else { /* According to PReP specification section 6.1.6 "System Interrupt * Assignments", all PCI interrupts are routed via IRQ 15 */ - s->or_irq =3D OR_IRQ(object_new(TYPE_OR_IRQ)); - object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PI= NS, + object_initialize_child(OBJECT(dev), "or-irq", &s->or_irq, TYPE_OR= _IRQ); + object_property_set_int(OBJECT(&s->or_irq), "num-lines", PCI_NUM_P= INS, &error_fatal); - qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal); - sysbus_init_irq(dev, &s->or_irq->out_irq); + qdev_realize(DEVICE(&s->or_irq), NULL, &error_fatal); + sysbus_init_irq(dev, &s->or_irq.out_irq); =20 for (i =3D 0; i < PCI_NUM_PINS; i++) { - s->pci_irqs[i] =3D qdev_get_gpio_in(DEVICE(s->or_irq), i); + s->pci_irqs[i] =3D qdev_get_gpio_in(DEVICE(&s->or_irq), i); } } =20 --=20 2.41.0