From nobody Fri Nov 1 07:35:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708064109; cv=none; d=zohomail.com; s=zohoarc; b=UY7/Eg1BcXJTlLQm9+xs+l1w/5Mh7C2RLjJUYV63JQmad/Mh1Ztcw+F+i698+nt0c9YyH90M0r+KWN3E3hkhif70+D5pfp+h5ISne8zP8g8cdJH/7WqUtV8kDUcS9op3nQQVwo+cMQ07hzVmMj4mFoPUr+d8S4w4UoC5go8/UF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708064109; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=itX+3OFXItueVSYXtwYhhb4zQIJ6apa53Hk8R5/2yuw=; b=cx4R3vAtqTyiKklX4ZYr2yINv2BM/XC4H4ZtejMyvwJHnccwDHRbr6A7xpGFJhvKxmCvBJvICCnQFGGAQ7AheBZu25H7idsfYAJr7ljoo4C/JizD2QNDUbygUxkQLSWxAmTzPqtOPT4WcOfMv7vHBbBfj/gx3r0iMB4Ug8hPWW0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708064109043589.234965881104; Thu, 15 Feb 2024 22:15:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rarUd-0001Qh-RR; Fri, 16 Feb 2024 01:14:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rarUc-0001P3-3Y for qemu-devel@nongnu.org; Fri, 16 Feb 2024 01:14:38 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rarUa-0006N6-8h for qemu-devel@nongnu.org; Fri, 16 Feb 2024 01:14:37 -0500 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 41G6EIQA007749; Fri, 16 Feb 2024 14:14:18 +0800 (+08) (envelope-from alvinga@andestech.com) Received: from alvinga-VirtualBox.andestech.com (10.0.13.68) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 16 Feb 2024 14:14:15 +0800 To: , CC: , , , , , Alvin Chang Subject: [PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode Date: Fri, 16 Feb 2024 14:13:31 +0800 Message-ID: <20240216061332.50229-4-alvinga@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216061332.50229-1-alvinga@andestech.com> References: <20240216061332.50229-1-alvinga@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.13.68] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 41G6EIQA007749 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=alvinga@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alvin Chang From: Alvin Chang via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708064110056100001 Content-Type: text/plain; charset="utf-8" From the RISC-V debug specification, it defines the following operations for CSR tcontrol when any trap into M-mode is taken: 1. tcontrol.MPTE is set to the value of tcontrol.MTE 2. tcontrol.MTE is set to 0 This commit implements the above operations into riscv_cpu_do_interrupt(). Signed-off-by: Alvin Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d462d95ee1..037ae21062 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1806,6 +1806,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_virt_enabled(env, 0); } =20 + /* Trapping to M-mode. Set tcontrol CSR in debug Sdtrig extension.= */ + s =3D env->tcontrol; + s =3D set_field(s, TCONTROL_MPTE, get_field(s, TCONTROL_MTE)); + s =3D set_field(s, TCONTROL_MTE, 0); + env->tcontrol =3D s; + s =3D env->mstatus; s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s =3D set_field(s, MSTATUS_MPP, env->priv); --=20 2.34.1