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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id u8-20020a170902a60800b001db5ee73fe9sm1618653plq.114.2024.02.15.11.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 11:28:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1708025322; x=1708630122; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PqJOdAFlOLuV8CILgRx55cvxXityDOLPppAKVjprA0M=; b=SR+6R8q8d+O9K5ZjJsH/LxdGOsB2RRGKTAifaG9fnl01MF8NA/sQvi1NngGKD/ff3k fRRYwD3wD3sgBfjR8zytGwS4UEt4z94w6AyY7mUrYyy++FAUr3pOJQ1o7XYI5vBF66wr /MEYXaIqXobrAJfW632Fk63vHNtsvYg4agNxeSSkhYJVt7DSai1vwAqbCSGdX9uml9/7 PuvbISa2ocHkOOPqgL3LpKAT9s81nymchZxbxLA6mx/KPMEuPqA6YQcd8HmU+Bbss3DL iK95ul/aS4b9vyTKSiKDOLGx5NwGJW0eBH+AlJo+q01O8OrFZ21HHtKpH+gYuiV7SwHX bzDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708025322; x=1708630122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PqJOdAFlOLuV8CILgRx55cvxXityDOLPppAKVjprA0M=; b=kJTMGRuSP64afwWexBnkCqHMA7LoGE2MP9ich39T597qOvKHNMembFXQzi9YfTnRFz VcSovY2PZZimag9mTHOZ9ylKtcEl03d+bWIIEi/6xskQWtjkzbync78a3VobIiCrp8sx 4TJ3wwsxvmAkiCriqJS3ICD/4YQ4Pkza9jwlj/cKuv4TiSeOTCUMPmibErXG/veyMgXW Xt72S4O6VfK2gOr6k92aSEsFlsivY6AKTnkG/46O0Wyv2AVoBRUra7ugEZ1Q0qVmIWyx VK8Ejs10a+vTgaySaMQwK2cOaJF6SQcL/ilR+Gvf2m1/7TkJjR9mVxlaSYxFj1e7JMaR +/vg== X-Gm-Message-State: AOJu0Yzqb0CNu0zm73f8enMyn0hM+V9OBYPjMXWp1/jxpwwfOhjJdjio QiT6Mk/0Xug8m85fvsF2uubVogYbJJ0G7vrsThXz9wEnNpf5YYU32IPsWexstTBFTpFTQ18WIFa CFqsRrUpzGi/KlrvX+W7nBI9f9I6UFQ/t499XFMqqX/F5qPwhQA8B4lxYl2DawB71FhLiAEg/SV e34uXTFgnfhuYSzInU+s6whMo7Wrj7zIKdS47iv7ec X-Google-Smtp-Source: AGHT+IGG99BIj2DOfKEYVErGN6NYizRM/krbGTsBNJ/Cse47yT3eBsPe+SAt74cbFA/GMmDjybeAuw== X-Received: by 2002:a17:902:8a96:b0:1d8:d5b0:aadb with SMTP id p22-20020a1709028a9600b001d8d5b0aadbmr2168871plo.66.1708025321984; Thu, 15 Feb 2024 11:28:41 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei Subject: [RFC PATCH 3/6] target/riscv: Inline vext_ldst_us and coressponding function for performance Date: Fri, 16 Feb 2024 03:28:14 +0800 Message-Id: <20240215192823.729209-4-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215192823.729209-1-max.chou@sifive.com> References: <20240215192823.729209-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=max.chou@sifive.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1708025401683100003 Content-Type: text/plain; charset="utf-8" In the vector unit-stride load/store helper functions. the vext_ldst_us function corresponding most of the execution time. Inline the functions can avoid the function call overhead to imperove the helper function performance. Signed-off-by: Max Chou Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e8fbb921449..866f77d321d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -149,25 +149,27 @@ static inline void vext_set_elem_mask(void *v0, int i= ndex, typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr, uint32_t idx, void *vd, uintptr_t retaddr); =20 -#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ -static void NAME(CPURISCVState *env, abi_ptr addr, \ - uint32_t idx, void *vd, uintptr_t retaddr)\ -{ \ - ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ - *cur =3D cpu_##LDSUF##_data_ra(env, addr, retaddr); \ -} \ +#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ +static inline QEMU_ALWAYS_INLINE \ +void NAME(CPURISCVState *env, abi_ptr addr, \ + uint32_t idx, void *vd, uintptr_t retaddr) \ +{ \ + ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ + *cur =3D cpu_##LDSUF##_data_ra(env, addr, retaddr); \ +} \ =20 GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb) GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw) GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl) GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq) =20 -#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ -static void NAME(CPURISCVState *env, abi_ptr addr, \ - uint32_t idx, void *vd, uintptr_t retaddr)\ -{ \ - ETYPE data =3D *((ETYPE *)vd + H(idx)); \ - cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ +#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ +static inline QEMU_ALWAYS_INLINE \ +void NAME(CPURISCVState *env, abi_ptr addr, \ + uint32_t idx, void *vd, uintptr_t retaddr) \ +{ \ + ETYPE data =3D *((ETYPE *)vd + H(idx)); \ + cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ } =20 GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb) @@ -289,7 +291,7 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) */ =20 /* unmasked unit-stride load and store operation */ -static void +static inline QEMU_ALWAYS_INLINE void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t des= c, vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl, uintptr_t ra) --=20 2.34.1