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Thu, 15 Feb 2024 10:01:48 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Cl=C3=A9ment=20Chigot?= , Frederic Konrad , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 35/56] hw/intc/grlib_irqmp: implements the multiprocessor status register Date: Thu, 15 Feb 2024 18:57:29 +0100 Message-ID: <20240215175752.82828-36-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708020274647100001 From: Cl=C3=A9ment Chigot This implements the multiprocessor status register in grlib-irqmp and bind it to a start signal, which will be later wired in leon3-generic to start a cpu. The EIRQ and BA bits are not implemented. Based on https://gaisler.com/doc/gr712rc-usermanual.pdf, =C2=A78.3.5. Co-developed-by: Frederic Konrad Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20240131085047.18458-4-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/grlib_irqmp.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 744cd64c58..1e073bd232 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -52,6 +52,10 @@ #define FORCE_OFFSET 0x80 #define EXTENDED_OFFSET 0xC0 =20 +/* Multiprocessor Status Register */ +#define MP_STATUS_CPU_STATUS_MASK ((1 << IRQMP_MAX_CPU)-2) +#define MP_STATUS_NCPU_SHIFT 28 + #define MAX_PILS 16 =20 OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP) @@ -65,6 +69,7 @@ struct IRQMP { =20 unsigned int ncpus; IRQMPState *state; + qemu_irq start_signal[IRQMP_MAX_CPU]; qemu_irq irq; }; =20 @@ -72,6 +77,7 @@ struct IRQMPState { uint32_t level; uint32_t pending; uint32_t clear; + uint32_t mpstatus; uint32_t broadcast; =20 uint32_t mask[IRQMP_MAX_CPU]; @@ -182,10 +188,12 @@ static uint64_t grlib_irqmp_read(void *opaque, hwaddr= addr, return state->force[0]; =20 case CLEAR_OFFSET: - case MP_STATUS_OFFSET: /* Always read as 0 */ return 0; =20 + case MP_STATUS_OFFSET: + return state->mpstatus; + case BROADCAST_OFFSET: return state->broadcast; =20 @@ -224,8 +232,9 @@ static uint64_t grlib_irqmp_read(void *opaque, hwaddr a= ddr, static void grlib_irqmp_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - IRQMP *irqmp =3D opaque; + IRQMP *irqmp =3D opaque; IRQMPState *state; + int i; =20 assert(irqmp !=3D NULL); state =3D irqmp->state; @@ -258,7 +267,18 @@ static void grlib_irqmp_write(void *opaque, hwaddr add= r, return; =20 case MP_STATUS_OFFSET: - /* Read Only (no SMP support) */ + /* + * Writing and reading operations are reversed for the CPU status. + * Writing "1" will start the CPU, but reading "1" means that the = CPU + * is power-down. + */ + value &=3D MP_STATUS_CPU_STATUS_MASK; + for (i =3D 0; i < irqmp->ncpus; i++) { + if ((value >> i) & 1) { + qemu_set_irq(irqmp->start_signal[i], 1); + state->mpstatus &=3D ~(1 << i); + } + } return; =20 case BROADCAST_OFFSET: @@ -325,6 +345,8 @@ static void grlib_irqmp_reset(DeviceState *d) =20 memset(irqmp->state, 0, sizeof *irqmp->state); irqmp->state->parent =3D irqmp; + irqmp->state->mpstatus =3D ((irqmp->ncpus - 1) << MP_STATUS_NCPU_SHIFT= ) | + ((1 << irqmp->ncpus) - 2); } =20 static void grlib_irqmp_realize(DeviceState *dev, Error **errp) @@ -338,6 +360,13 @@ static void grlib_irqmp_realize(DeviceState *dev, Erro= r **errp) } =20 qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS); + + /* + * Transitionning from 0 to 1 starts the CPUs. The opposite can't + * happen. + */ + qdev_init_gpio_out_named(dev, irqmp->start_signal, "grlib-start-cpu", + IRQMP_MAX_CPU); qdev_init_gpio_out_named(dev, &irqmp->irq, "grlib-irq", 1); memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, ir= qmp, "irqmp", IRQMP_REG_SIZE); --=20 2.41.0