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Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Subject: [PULL 22/56] hw/i386/q35: Realize LPC PCI function before accessing it Date: Thu, 15 Feb 2024 18:57:16 +0100 Message-ID: <20240215175752.82828-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708020325128100005 We should not wire IRQs on unrealized device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Damien Hedde Reviewed-by: BALATON Zoltan Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-5-philmd@linaro.org> --- hw/i386/pc_q35.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 7ca3f465e0..b7c69d55d6 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -248,13 +248,13 @@ static void pc_q35_init(MachineState *machine) /* create ISA bus */ lpc =3D pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), TYPE_ICH9_LPC_DEVICE); - qdev_prop_set_bit(DEVICE(lpc), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); lpc_dev =3D DEVICE(lpc); + qdev_prop_set_bit(lpc_dev, "smm-enabled", + x86_machine_is_smm_enabled(x86ms)); + pci_realize_and_unref(lpc, host_bus, &error_fatal); for (i =3D 0; i < IOAPIC_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[= i]); } - pci_realize_and_unref(lpc, host_bus, &error_fatal); =20 rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "r= tc")); =20 --=20 2.41.0