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Thu, 15 Feb 2024 09:58:53 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang Subject: [PULL 09/56] hw/misc/mips_itu: Remove MIPSITUState::saar field Date: Thu, 15 Feb 2024 18:57:03 +0100 Message-ID: <20240215175752.82828-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708020011074100001 This field is not set. Remove it along with the dead code it was guarding. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-7-philmd@linaro.org> --- include/hw/misc/mips_itu.h | 3 --- hw/misc/mips_itu.c | 22 +++------------------- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index de7400c1fe..27c9a1090d 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -70,9 +70,6 @@ struct MIPSITUState { =20 /* ITU Control Register */ uint64_t icr0; - - /* SAAR */ - uint64_t *saar; }; =20 /* Get ITC Configuration Tag memory region. */ diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 9705efeafe..f8acfb3ee2 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -94,12 +94,6 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 - if (tag->saar) { - address =3D (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; - size =3D 1ULL << ((tag->saar[0] >> 1) & 0x1f); - is_enabled =3D tag->saar[0] & 1; - } - memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); @@ -158,12 +152,7 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain =3D 0) is 128 B */ - if (s->saar) { - return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & - ITC_ICR0_BLK_GRAIN_MASK); - } else { - return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); - } + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); } =20 static inline ITCStorageCell *get_cell(MIPSITUState *s, @@ -535,15 +524,10 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s =3D MIPS_ITU(dev); =20 - if (s->saar) { - s->saar[0] =3D 0x11 << 1; - s->icr0 =3D get_num_cells(s) << ITC_ICR0_CELL_NUM; - } else { - s->ITCAddressMap[0] =3D 0; - s->ITCAddressMap[1] =3D + s->ITCAddressMap[0] =3D 0; + s->ITCAddressMap[1] =3D ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); - } itc_reconfigure(s); =20 itc_reset_cells(s); --=20 2.41.0