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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
Date: Thu, 15 Feb 2024 17:35:09 +0000
Message-Id: <20240215173538.2430599-7-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
These functions "use the standard load helpers", but
fail to clean_data_tbi or populate mtedesc.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 508f7b6bbdc..ada05aa5302 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4861,8 +4861,13 @@ static void do_ldrq(DisasContext *s, int zt, int pg,=
TCGv_i64 addr, int dtype)
unsigned vsz =3D vec_full_reg_size(s);
TCGv_ptr t_pg;
int poff;
+ uint32_t desc;
=20
/* Load the first quadword using the normal predicated load helpers. =
*/
+ if (!s->mte_active[0]) {
+ addr =3D clean_data_tbi(s, addr);
+ }
+
poff =3D pred_full_reg_offset(s, pg);
if (vsz > 16) {
/*
@@ -4886,7 +4891,8 @@ static void do_ldrq(DisasContext *s, int zt, int pg, =
TCGv_i64 addr, int dtype)
=20
gen_helper_gvec_mem *fn
=3D ldr_fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][dtype][0];
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
+ desc =3D make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
=20
/* Replicate that first quadword. */
if (vsz > 16) {
@@ -4929,6 +4935,7 @@ static void do_ldro(DisasContext *s, int zt, int pg, =
TCGv_i64 addr, int dtype)
unsigned vsz_r32;
TCGv_ptr t_pg;
int poff, doff;
+ uint32_t desc;
=20
if (vsz < 32) {
/*
@@ -4941,6 +4948,9 @@ static void do_ldro(DisasContext *s, int zt, int pg, =
TCGv_i64 addr, int dtype)
}
=20
/* Load the first octaword using the normal predicated load helpers. =
*/
+ if (!s->mte_active[0]) {
+ addr =3D clean_data_tbi(s, addr);
+ }
=20
poff =3D pred_full_reg_offset(s, pg);
if (vsz > 32) {
@@ -4965,7 +4975,8 @@ static void do_ldro(DisasContext *s, int zt, int pg, =
TCGv_i64 addr, int dtype)
=20
gen_helper_gvec_mem *fn
=3D ldr_fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][dtype][0];
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
+ desc =3D make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
=20
/*
* Replicate that first octaword.
--=20
2.34.1