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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
Date: Thu, 15 Feb 2024 17:35:06 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The field is encoded as [0-3], which is convenient for
indexing our array of function pointers, but the true
value is [1-4]. Adjust before calling do_mem_zpa.
Add an assert, and move the comment re passing ZT to
the helper back next to the relevant code.
Cc: qemu-stable@nongnu.org
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads=
")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-sve.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 296e7d1ce22..7108938251e 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4445,11 +4445,7 @@ static void do_mem_zpa(DisasContext *s, int zt, int =
pg, TCGv_i64 addr,
TCGv_ptr t_pg;
int desc =3D 0;
=20
- /*
- * For e.g. LD4, there are not enough arguments to pass all 4
- * registers as pointers, so encode the regno into the data field.
- * For consistency, do this even for LD1.
- */
+ assert(mte_n >=3D 1 && mte_n <=3D 4);
if (s->mte_active[0]) {
int msz =3D dtype_msz(dtype);
=20
@@ -4463,6 +4459,11 @@ static void do_mem_zpa(DisasContext *s, int zt, int =
pg, TCGv_i64 addr,
addr =3D clean_data_tbi(s, addr);
}
=20
+ /*
+ * For e.g. LD4, there are not enough arguments to pass all 4
+ * registers as pointers, so encode the regno into the data field.
+ * For consistency, do this even for LD1.
+ */
desc =3D simd_desc(vsz, vsz, zt | desc);
t_pg =3D tcg_temp_new_ptr();
=20
@@ -4600,7 +4601,7 @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
* accessible via the instruction encoding.
*/
assert(fn !=3D NULL);
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
}
=20
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
@@ -5168,14 +5169,13 @@ static void do_st_zpa(DisasContext *s, int zt, int =
pg, TCGv_i64 addr,
if (nreg =3D=3D 0) {
/* ST1 */
fn =3D fn_single[s->mte_active[0]][be][msz][esz];
- nreg =3D 1;
} else {
/* ST2, ST3, ST4 -- msz =3D=3D esz, enforced by encoding */
assert(msz =3D=3D esz);
fn =3D fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
}
assert(fn !=3D NULL);
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
}
=20
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
--=20
2.34.1