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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE
 mode
Date: Thu, 15 Feb 2024 17:35:05 +0000
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From: Richard Henderson <richard.henderson@linaro.org>

The API does not generate an error for setting ASYNC | SYNC; that merely
constrains the selection vs the per-cpu default.  For qemu linux-user,
choose SYNC as the default.

Cc: qemu-stable@nongnu.org
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_=
prctl.h
index 5067e7d7310..aa8e203c153 100644
--- a/linux-user/aarch64/target_prctl.h
+++ b/linux-user/aarch64/target_prctl.h
@@ -173,21 +173,26 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArch=
State *env, abi_long arg2)
     env->tagged_addr_enable =3D arg2 & PR_TAGGED_ADDR_ENABLE;
=20
     if (cpu_isar_feature(aa64_mte, cpu)) {
-        switch (arg2 & PR_MTE_TCF_MASK) {
-        case PR_MTE_TCF_NONE:
-        case PR_MTE_TCF_SYNC:
-        case PR_MTE_TCF_ASYNC:
-            break;
-        default:
-            return -EINVAL;
-        }
-
         /*
          * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
-         * Note that the syscall values are consistent with hw.
+         *
+         * The kernel has a per-cpu configuration for the sysadmin,
+         * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
+         * which qemu does not implement.
+         *
+         * Because there is no performance difference between the modes, a=
nd
+         * because SYNC is most useful for debugging MTE errors, choose SY=
NC
+         * as the preferred mode.  With this preference, and the way the A=
PI
+         * uses only two bits, there is no way for the program to select
+         * ASYMM mode.
          */
-        env->cp15.sctlr_el[1] =3D
-            deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHI=
FT);
+        unsigned tcf =3D 0;
+        if (arg2 & PR_MTE_TCF_SYNC) {
+            tcf =3D 1;
+        } else if (arg2 & PR_MTE_TCF_ASYNC) {
+            tcf =3D 2;
+        }
+        env->cp15.sctlr_el[1] =3D deposit64(env->cp15.sctlr_el[1], 38, 2, =
tcf);
=20
         /*
          * Write PR_MTE_TAG to GCR_EL1[Exclude].
--=20
2.34.1