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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in
upstream QEMU
Date: Thu, 15 Feb 2024 17:35:20 +0000
Message-Id: <20240215173538.2430599-18-peter.maydell@linaro.org>
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From: Nabih Estefan <nabihestefan@google.com>
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
of 8xx. Also fix comments referencing this and values expecting 8xx.
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
tests/qtest/meson.build | 3 +-
2 files changed, 4 insertions(+), 83 deletions(-)
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
index 9e58b15ca1c..c28b471ab20 100644
--- a/tests/qtest/npcm_gmac-test.c
+++ b/tests/qtest/npcm_gmac-test.c
@@ -36,7 +36,7 @@ typedef struct TestData {
const GMACModule *module;
} TestData;
=20
-/* Values extracted from hw/arm/npcm8xx.c */
+/* Values extracted from hw/arm/npcm7xx.c */
static const GMACModule gmac_module_list[] =3D {
{
.irq =3D 14,
@@ -46,14 +46,6 @@ static const GMACModule gmac_module_list[] =3D {
.irq =3D 15,
.base_addr =3D 0xf0804000
},
- {
- .irq =3D 16,
- .base_addr =3D 0xf0806000
- },
- {
- .irq =3D 17,
- .base_addr =3D 0xf0808000
- }
};
=20
/* Returns the index of the GMAC module. */
@@ -182,32 +174,18 @@ static uint32_t gmac_read(QTestState *qts, const GMAC=
Module *mod,
return qtest_readl(qts, mod->base_addr + regno);
}
=20
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
- NPCMRegister regno)
-{
- uint32_t write_value =3D (regno & 0x3ffe00) >> 9;
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
- uint32_t read_offset =3D regno & 0x1ff;
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
-}
-
/* Check that GMAC registers are reset to default value */
static void test_init(gconstpointer test_data)
{
const TestData *td =3D test_data;
const GMACModule *mod =3D td->module;
- QTestState *qts =3D qtest_init("-machine npcm845-evb");
+ QTestState *qts =3D qtest_init("-machine npcm750-evb");
=20
#define CHECK_REG32(regno, value) \
do { \
g_assert_cmphex(gmac_read(qts, mod, (regno)), =3D=3D, (value)); \
} while (0)
=20
-#define CHECK_REG_PCS(regno, value) \
- do { \
- g_assert_cmphex(pcs_read(qts, mod, (regno)), =3D=3D, (value)); \
- } while (0)
-
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
@@ -257,64 +235,6 @@ static void test_init(gconstpointer test_data)
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
=20
- /* TODO Add registers PCS */
- if (mod->base_addr =3D=3D 0xf0802000) {
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
-
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
-
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
-
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
- }
-
qtest_quit(qts);
}
=20
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 663338ae124..2b89e8634be 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -192,7 +192,8 @@ qtests_npcm7xx =3D \
'npcm7xx_sdhci-test',
'npcm7xx_smbus-test',
'npcm7xx_timer-test',
- 'npcm7xx_watchdog_timer-test'] + \
+ 'npcm7xx_watchdog_timer-test',
+ 'npcm_gmac-test'] + \
(slirp.found() ? ['npcm7xx_emc-test'] : [])
qtests_aspeed =3D \
['aspeed_hace-test',
--=20
2.34.1