From nobody Fri Nov 1 05:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708009351; cv=none; d=zohomail.com; s=zohoarc; b=EF+dWzB3B2/pjXpfB0iXVLlz0G3TaLDRbYn6IyLL5q4hD2SUYmBDU31s+Xti0oCQ8VydDMooQ1TsBHjOo1WwIiR0Lm98PMdRYSBSt3pii3IITnE9ShPNt6Sf/U+gEO3vHNtpjK9USg6Cpf0THVRFuS7fQv7hSVbtM75N2c9OlBU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708009351; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=YM0Q7LiX/iuxbBPomBKPDdFJGpuMlrfqF4fK+qszsuU=; b=Ndj8DwIV3EqZTNJ89AXRiFiblCZ7Z2y+rTgOGV4rGBueIDXF9/tTBErjNinpFGZBEFjhnBJk2OdQYo09sMzXkkLdW0TfL+CWDTqs9OvaIgxQNmhu5s6uB5MuXvpy1+gbzNNlSSG0RqnEgImColqxNsY+3GwQ9zjTk2Q/GVwo7tE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708009351646768.4313599537649; Thu, 15 Feb 2024 07:02:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1radFk-0004Qa-E7; Thu, 15 Feb 2024 10:02:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1radFi-0004Pl-NI for qemu-devel@nongnu.org; Thu, 15 Feb 2024 10:02:18 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1radFb-0001xv-MS for qemu-devel@nongnu.org; Thu, 15 Feb 2024 10:02:18 -0500 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4TbJ981cwqz6K8Xc; Thu, 15 Feb 2024 22:58:36 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (unknown [7.191.163.240]) by mail.maildlp.com (Postfix) with ESMTPS id 06233140DAF; Thu, 15 Feb 2024 23:02:04 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 15 Feb 2024 15:02:03 +0000 To: , Peter Maydell , Gregory Price , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Sajjan Rao , Dimitrios Palyvos , , Paolo Bonzini , Eduardo Habkost CC: Subject: [PATCH 1/3] accel/tcg: Set can_do_io at at start of lookup_tb_ptr helper Date: Thu, 15 Feb 2024 15:01:31 +0000 Message-ID: <20240215150133.2088-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240215150133.2088-1-Jonathan.Cameron@huawei.com> References: <20240215150133.2088-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500005.china.huawei.com (7.191.163.240) To lhrpeml500005.china.huawei.com (7.191.163.240) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708009352910100001 Content-Type: text/plain; charset="utf-8" From: Peter Maydell Peter posted this in the thread trying to fix x86 TCG handling of page tables in MMIO space (specifically emulated CXL interleaved memory) https://lore.kernel.org/qemu-devel/CAFEAcA_a_AyQ=3DEpz3_+CheAT8Crsk9mOu894w= bNW_FywamkZiw@mail.gmail.com/#t Peter, are you happy to give your SoB on this one? Signed-off-by: Jonathan Cameron Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 977576ca14..52239a441f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -396,6 +396,14 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) uint64_t cs_base; uint32_t flags, cflags; =20 + /* + * By definition we've just finished a TB, so I/O is OK. + * Avoid the possibility of calling cpu_io_recompile() if + * a page table walk triggered by tb_lookup() calling + * probe_access_internal() happens to touch an MMIO device. + * The next TB, if we chain to it, will clear the flag again. + */ + cpu->neg.can_do_io =3D true; cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 cflags =3D curr_cflags(cpu); --=20 2.39.2 From nobody Fri Nov 1 05:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 15 Feb 2024 23:02:34 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 15 Feb 2024 15:02:34 +0000 To: , Peter Maydell , Gregory Price , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Sajjan Rao , Dimitrios Palyvos , , Paolo Bonzini , Eduardo Habkost CC: Subject: [PATCH 2/3] target/i386: Enable page walking from MMIO memory Date: Thu, 15 Feb 2024 15:01:32 +0000 Message-ID: <20240215150133.2088-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240215150133.2088-1-Jonathan.Cameron@huawei.com> References: <20240215150133.2088-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500005.china.huawei.com (7.191.163.240) To lhrpeml500005.china.huawei.com (7.191.163.240) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_PORT=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708009394975100001 Content-Type: text/plain; charset="utf-8" From: Gregory Price CXL emulation of interleave requires read and write hooks due to requirement for subpage granularity. The Linux kernel stack now enables using this memory as conventional memory in a separate NUMA node. If a process is deliberately forced to run from that node $ numactl --membind=3D1 ls the page table walk on i386 fails. Useful part of backtrace: (cpu=3Dcpu@entry=3D0x555556fd9000, fmt=3Dfmt@entry=3D0x555555fe3378 "cp= u_io_recompile: could not find TB for pc=3D%p") at ../../cpu-target.c:359 (retaddr=3D0, addr=3D19595792376, attrs=3D..., xlat=3D, = cpu=3D0x555556fd9000, out_offset=3D) at ../../accel/tcg/cputlb.c:1339 (cpu=3D0x555556fd9000, full=3D0x7fffee0d96e0, ret_be=3Dret_be@entry=3D0= , addr=3D19595792376, size=3Dsize@entry=3D8, mmu_idx=3D4, type=3DMMU_DATA_L= OAD, ra=3D0) at ../../accel/tcg/cputlb.c:2030 (cpu=3Dcpu@entry=3D0x555556fd9000, p=3Dp@entry=3D0x7ffff56fddc0, mmu_id= x=3D, type=3Dtype@entry=3DMMU_DATA_LOAD, memop=3D, ra=3Dra@entry=3D0) at ../../accel/tcg/cputlb.c:2356 (cpu=3Dcpu@entry=3D0x555556fd9000, addr=3Daddr@entry=3D19595792376, oi= =3Doi@entry=3D52, ra=3Dra@entry=3D0, access_type=3Daccess_type@entry=3DMMU_= DATA_LOAD) at ../../accel/tcg/cputlb.c:2439 at ../../accel/tcg/ldst_common.c.inc:301 at ../../target/i386/tcg/sysemu/excp_helper.c:173 (err=3D0x7ffff56fdf80, out=3D0x7ffff56fdf70, mmu_idx=3D0, access_type= =3DMMU_INST_FETCH, addr=3D18446744072116178925, env=3D0x555556fdb7c0) at ../../target/i386/tcg/sysemu/excp_helper.c:578 (cs=3D0x555556fd9000, addr=3D18446744072116178925, size=3D, access_type=3DMMU_INST_FETCH, mmu_idx=3D0, probe=3D, ret= addr=3D0) at ../../target/i386/tcg/sysemu/excp_helper.c:604 Avoid this by plumbing the address all the way down from x86_cpu_tlb_fill() where is available as retaddr to the actual accessors which provide it to probe_access_full() which already handles MMIO accesses. Signed-off-by: Gregory Price Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Suggested-by: Peter Maydell --- Patch posted in reply to thread: https://lore.kernel.org/qemu-devel/ZbvpSaOXzZkqDd6c@memverge.com/ I checked Gregory was fine with me adding Sign-off / author via the CXL dis= cord. --- target/i386/tcg/sysemu/excp_helper.c | 57 +++++++++++++++------------- 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 5b86f439ad..b3bce020f4 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -59,14 +59,14 @@ typedef struct PTETranslate { hwaddr gaddr; } PTETranslate; =20 -static bool ptw_translate(PTETranslate *inout, hwaddr addr) +static bool ptw_translate(PTETranslate *inout, hwaddr addr, uint64_t ra) { CPUTLBEntryFull *full; int flags; =20 inout->gaddr =3D addr; flags =3D probe_access_full(inout->env, addr, 0, MMU_DATA_STORE, - inout->ptw_idx, true, &inout->haddr, &full, = 0); + inout->ptw_idx, true, &inout->haddr, &full, = ra); =20 if (unlikely(flags & TLB_INVALID_MASK)) { TranslateFault *err =3D inout->err; @@ -82,20 +82,20 @@ static bool ptw_translate(PTETranslate *inout, hwaddr a= ddr) return true; } =20 -static inline uint32_t ptw_ldl(const PTETranslate *in) +static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra) { if (likely(in->haddr)) { return ldl_p(in->haddr); } - return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); + return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } =20 -static inline uint64_t ptw_ldq(const PTETranslate *in) +static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra) { if (likely(in->haddr)) { return ldq_p(in->haddr); } - return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); + return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } =20 /* @@ -132,7 +132,8 @@ static inline bool ptw_setl(const PTETranslate *in, uin= t32_t old, uint32_t set) } =20 static bool mmu_translate(CPUX86State *env, const TranslateParams *in, - TranslateResult *out, TranslateFault *err) + TranslateResult *out, TranslateFault *err, + uint64_t ra) { const int32_t a20_mask =3D x86_get_a20_mask(env); const target_ulong addr =3D in->addr; @@ -166,11 +167,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_5: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -191,11 +192,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_4: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -212,11 +213,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_3_lma: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -239,12 +240,12 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, * Page table level 3 */ pte_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20= _mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } rsvd_mask |=3D PG_HI_USER_MASK; restart_3_nolma: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -262,11 +263,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_2_pae: - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -289,10 +290,10 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } - pte =3D ptw_ldq(&pte_trans); + pte =3D ptw_ldq(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -307,11 +308,11 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, * Page table level 2 */ pte_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_m= ask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } restart_2_nopae: - pte =3D ptw_ldl(&pte_trans); + pte =3D ptw_ldl(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -336,10 +337,10 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, * Page table level 1 */ pte_addr =3D ((pte & ~0xfffu) + ((addr >> 10) & 0xffc)) & a20_mask; - if (!ptw_translate(&pte_trans, pte_addr)) { + if (!ptw_translate(&pte_trans, pte_addr, ra)) { return false; } - pte =3D ptw_ldl(&pte_trans); + pte =3D ptw_ldl(&pte_trans, ra); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -529,7 +530,8 @@ static G_NORETURN void raise_stage2(CPUX86State *env, T= ranslateFault *err, =20 static bool get_physical_address(CPUX86State *env, vaddr addr, MMUAccessType access_type, int mmu_idx, - TranslateResult *out, TranslateFault *err) + TranslateResult *out, TranslateFault *err, + uint64_t ra) { TranslateParams in; bool use_stage2 =3D env->hflags2 & HF2_NPT_MASK; @@ -548,7 +550,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, in.mmu_idx =3D MMU_USER_IDX; in.ptw_idx =3D MMU_PHYS_IDX; =20 - if (!mmu_translate(env, &in, out, err)) { + if (!mmu_translate(env, &in, out, err, ra)) { err->stage2 =3D S2_GPA; return false; } @@ -575,7 +577,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, return false; } } - return mmu_translate(env, &in, out, err); + return mmu_translate(env, &in, out, err, ra); } break; } @@ -601,7 +603,8 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int siz= e, TranslateResult out; TranslateFault err; =20 - if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err))= { + if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err, + retaddr)) { /* * Even if 4MB pages, we map only one 4KB page in the cache to * avoid filling it too fast. --=20 2.39.2 From nobody Fri Nov 1 05:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708009419; cv=none; d=zohomail.com; s=zohoarc; b=fd6KzyRClRfsTWzCR7B4yNcj42M4R/vCvxXn3LwWF29RLXKhFKzVPZrYe4drK+3CDneISNvl+YIOBjSQPxuDT1kbGumgPUoeWtIXTZev1ETK2qNMibQpjr0XsHj0/qo4MyCmtoH/ZFRBjGLVSWhLb0hGFn6FQ5XDUHuwLHYAPow= ARC-Message-Signature: i=1; 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Thu, 15 Feb 2024 15:03:04 +0000 To: , Peter Maydell , Gregory Price , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Sajjan Rao , Dimitrios Palyvos , , Paolo Bonzini , Eduardo Habkost CC: Subject: [PATCH 3/3] tcg: Avoid double lock if page tables happen to be in mmio memory. Date: Thu, 15 Feb 2024 15:01:33 +0000 Message-ID: <20240215150133.2088-4-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240215150133.2088-1-Jonathan.Cameron@huawei.com> References: <20240215150133.2088-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500005.china.huawei.com (7.191.163.240) To lhrpeml500005.china.huawei.com (7.191.163.240) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1708009421082100003 Content-Type: text/plain; charset="utf-8" On i386, after fixing the page walking code to work with pages in MMIO memory (specifically CXL emulated interleaved memory), a crash was seen in an interrupt handling path. Useful part of bt Peter identified this as being due to the BQL already being held when the page table walker encounters MMIO memory and attempts to take the lock again. There are other examples of similar paths TCG, so this follows the approach taken in those of simply checking if the lock is already held and if it is, don't take it again. Suggested-by: Peter Maydell Signed-off-by: Jonathan Cameron --- accel/tcg/cputlb.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 047cd2cc0a..3b8d178707 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2019,6 +2019,7 @@ static uint64_t do_ld_mmio_beN(CPUState *cpu, CPUTLBE= ntryFull *full, int mmu_idx, MMUAccessType type, uintptr_t = ra) { MemoryRegionSection *section; + bool locked =3D bql_locked(); MemoryRegion *mr; hwaddr mr_offset; MemTxAttrs attrs; @@ -2030,10 +2031,14 @@ static uint64_t do_ld_mmio_beN(CPUState *cpu, CPUTL= BEntryFull *full, section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); mr =3D section->mr; =20 - bql_lock(); + if (!locked) { + bql_lock(); + } ret =3D int_ld_mmio_beN(cpu, full, ret_be, addr, size, mmu_idx, type, ra, mr, mr_offset); - bql_unlock(); + if (!locked) { + bql_unlock(); + } =20 return ret; } --=20 2.39.2