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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id qc14-20020a17090b288e00b0029900404e11sm807755pjb.27.2024.02.15.00.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 00:14:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707984893; x=1708589693; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r70v09Z1jYUdUmudZIEve8pIi40latYcxErAtIALfYA=; b=awE855qcctlZwnzAHPxC0TDCZW+3k7eu29biOnePABpynBxx8W4+IkEmcfczHkP0/f 88UWPFms5GZbajhPIWwi+2anMUEPCgW+j3kjrBun6DebIE3/PHKHDX7Z0UmqpdnPtB2D LS8AB1ysQFKNp/AHEcxQDr1+pRRsY1g36jzsi5ImhAiQHGdUOHVyq2n9A6hRMDbTYSMr q//6QQMHkB2riWQES0YOLEztexu8ewEb+OY8Q4dBx9zIZzewX5lv0/nIWLWCbYSABis/ 4t9r0gtqfIVQ+DkhhDKN3Guj5IP2TFj+SdxlQEQNhqdH5RViX53C2ZtHj2qDG+ecLpfg Vcdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707984893; x=1708589693; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r70v09Z1jYUdUmudZIEve8pIi40latYcxErAtIALfYA=; b=hFqxsgEpKDueKx7FseqHYOi7l/M54ormWoR/qK9i0meA+pv69yESnfZCmtqDZG+bjA v4mnV2YFThISK2JNXrdFi8LraGqAATHgd37KIfLIFhmzGoncrOf3GPBVM16BLKYXx5De mazMCsV+e3PBZjF4IDhQBLhBYMC90LKbTpkuW+qkg2YDJY3771DyUJXtKYdMhXnkWsyn qlCjl1X9hkM2O/z8ZkqR5kb4/ELgKZr2MKwKNzQ8jArOTrcxoRRvcBvbye2iU20x+jvg 8qYYC1rwg3kKyFHSPWeDfVozD8hEEzks72hrZTKxzx49K7POe8tc4tQmVEmLzMoneFqj F1sQ== X-Gm-Message-State: AOJu0YxUbcvMvTwXLJRWzs2beUOiEblbDmXxdqDWdmR/XeYQLdShaMuM hp24M9B3JrW3JMMVPQKoJ2APZ1NiYgwAOZYCxb06x2NqCWBkY7FmPEHtkecvnQKG2SodH5K2aDX 0 X-Google-Smtp-Source: AGHT+IEjzEpF95iRu04ODMPmpwiAGhUUMEgRkWSdaJ1h07KcMKHTxihRPUyIoG/pSXtgxIoOYveB0w== X-Received: by 2002:a17:90b:4a02:b0:299:17a7:c443 with SMTP id kk2-20020a17090b4a0200b0029917a7c443mr274265pjb.32.1707984893328; Thu, 15 Feb 2024 00:14:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: amonakov@ispras.ru, mmromanov@ispras.ru Subject: [PATCH v4 01/10] util/bufferiszero: Remove SSE4.1 variant Date: Wed, 14 Feb 2024 22:14:40 -1000 Message-Id: <20240215081449.848220-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215081449.848220-1-richard.henderson@linaro.org> References: <20240215081449.848220-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707985007766100001 Content-Type: text/plain; charset="utf-8" From: Alexander Monakov The SSE4.1 variant is virtually identical to the SSE2 variant, except for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing if an SSE register is all zeroes. The PTEST instruction decodes to two uops, so it can be handled only by the complex decoder, and since CMP+JNE are macro-fused, both sequences decode to three uops. The uops comprising the PTEST instruction dispatch to p0 and p5 on Intel CPUs, so PCMPEQB+PMOVMSKB is comparatively more flexible from dispatch standpoint. Hence, the use of PTEST brings no benefit from throughput standpoint. Its latency is not important, since it feeds only a conditional jump, which terminates the dependency chain. I never observed PTEST variants to be faster on real hardware. Signed-off-by: Alexander Monakov Signed-off-by: Mikhail Romanov Reviewed-by: Richard Henderson Message-Id: <20240206204809.9859-2-amonakov@ispras.ru> --- util/bufferiszero.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/util/bufferiszero.c b/util/bufferiszero.c index 3e6a5dfd63..f5a3634f9a 100644 --- a/util/bufferiszero.c +++ b/util/bufferiszero.c @@ -100,34 +100,6 @@ buffer_zero_sse2(const void *buf, size_t len) } =20 #ifdef CONFIG_AVX2_OPT -static bool __attribute__((target("sse4"))) -buffer_zero_sse4(const void *buf, size_t len) -{ - __m128i t =3D _mm_loadu_si128(buf); - __m128i *p =3D (__m128i *)(((uintptr_t)buf + 5 * 16) & -16); - __m128i *e =3D (__m128i *)(((uintptr_t)buf + len) & -16); - - /* Loop over 16-byte aligned blocks of 64. */ - while (likely(p <=3D e)) { - __builtin_prefetch(p); - if (unlikely(!_mm_testz_si128(t, t))) { - return false; - } - t =3D p[-4] | p[-3] | p[-2] | p[-1]; - p +=3D 4; - } - - /* Finish the aligned tail. */ - t |=3D e[-3]; - t |=3D e[-2]; - t |=3D e[-1]; - - /* Finish the unaligned tail. */ - t |=3D _mm_loadu_si128(buf + len - 16); - - return _mm_testz_si128(t, t); -} - static bool __attribute__((target("avx2"))) buffer_zero_avx2(const void *buf, size_t len) { @@ -221,7 +193,6 @@ select_accel_cpuinfo(unsigned info) #endif #ifdef CONFIG_AVX2_OPT { CPUINFO_AVX2, 128, buffer_zero_avx2 }, - { CPUINFO_SSE4, 64, buffer_zero_sse4 }, #endif { CPUINFO_SSE2, 64, buffer_zero_sse2 }, { CPUINFO_ALWAYS, 0, buffer_zero_int }, --=20 2.34.1