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Tsirkin" , Paolo Bonzini , qemu-block@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Aleksandar Rikalo Subject: [PATCH 3/9] hw/ide/ahci: Rename AHCI PCI function as 'pdev' Date: Tue, 13 Feb 2024 09:11:54 +0100 Message-ID: <20240213081201.78951-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240213081201.78951-1-philmd@linaro.org> References: <20240213081201.78951-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707812031968100003 We want to access AHCIPCIState::ahci field. In order to keep the code simple (avoiding &ahci->ahci), rename the current 'ahci' variable as 'pdev' Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/pc_q35.c | 15 ++++++++------- hw/mips/boston.c | 10 +++++----- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index ace8d3839a..e298f4ff32 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -135,7 +135,6 @@ static void pc_q35_init(MachineState *machine) GSIState *gsi_state; ISABus *isa_bus; int i; - PCIDevice *ahci; ram_addr_t lowmem; DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc =3D MACHINE_GET_CLASS(machine); @@ -304,16 +303,18 @@ static void pc_q35_init(MachineState *machine) 0xff0104); =20 if (pcms->sata_enabled) { + PCIDevice *pdev; + /* ahci and SATA device, for q35 1 ahci controller is built-in */ - ahci =3D pci_create_simple_multifunction(host_bus, + pdev =3D pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); - idebus[0] =3D qdev_get_child_bus(DEVICE(ahci), "ide.0"); - idebus[1] =3D qdev_get_child_bus(DEVICE(ahci), "ide.1"); - g_assert(MAX_SATA_PORTS =3D=3D ahci_get_num_ports(ahci)); - ide_drive_get(hd, ahci_get_num_ports(ahci)); - ahci_ide_create_devs(ahci, hd); + idebus[0] =3D qdev_get_child_bus(DEVICE(pdev), "ide.0"); + idebus[1] =3D qdev_get_child_bus(DEVICE(pdev), "ide.1"); + g_assert(MAX_SATA_PORTS =3D=3D ahci_get_num_ports(pdev)); + ide_drive_get(hd, ahci_get_num_ports(pdev)); + ahci_ide_create_devs(pdev, hd); } else { idebus[0] =3D idebus[1] =3D NULL; } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index cbcefdd693..0ec0b98066 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -677,7 +677,7 @@ static void boston_mach_init(MachineState *machine) MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; MemoryRegion *sys_mem =3D get_system_memory(); XilinxPCIEHost *pcie2; - PCIDevice *ahci; + PCIDevice *pdev; DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; @@ -769,11 +769,11 @@ static void boston_mach_init(MachineState *machine) qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, boston_lcd_event, NULL, s, NULL, true); =20 - ahci =3D pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->se= c_bus, + pdev =3D pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->se= c_bus, PCI_DEVFN(0, 0), TYPE_ICH9_AHCI= ); - g_assert(ARRAY_SIZE(hd) =3D=3D ahci_get_num_ports(ahci)); - ide_drive_get(hd, ahci_get_num_ports(ahci)); - ahci_ide_create_devs(ahci, hd); + g_assert(ARRAY_SIZE(hd) =3D=3D ahci_get_num_ports(pdev)); + ide_drive_get(hd, ahci_get_num_ports(pdev)); + ahci_ide_create_devs(pdev, hd); =20 if (machine->firmware) { fw_size =3D load_image_targphys(machine->firmware, --=20 2.41.0