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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled Date: Tue, 13 Feb 2024 05:19:52 +0100 Message-ID: <20240213041952.58840-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707798062190100001 We can not create the Q35 machine without PCI, so simplify pc_q35_init() removing pointless checks. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/i386/pc_q35.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 7ca3f465e0..5923621845 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -130,8 +130,7 @@ static void pc_q35_init(MachineState *machine) ISADevice *rtc_state; MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *system_io =3D get_system_io(); - MemoryRegion *pci_memory; - MemoryRegion *rom_memory; + MemoryRegion *pci_memory =3D g_new(MemoryRegion, 1); GSIState *gsi_state; ISABus *isa_bus; int i; @@ -143,6 +142,8 @@ static void pc_q35_init(MachineState *machine) bool keep_pci_slot_hpc; uint64_t pci_hole64_size =3D 0; =20 + assert(pcmc->pci_enabled); + /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping * also known as MMCFG). @@ -189,16 +190,6 @@ static void pc_q35_init(MachineState *machine) kvmclock_create(pcmc->kvmclock_create_always); } =20 - /* pci enabled */ - if (pcmc->pci_enabled) { - pci_memory =3D g_new(MemoryRegion, 1); - memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); - rom_memory =3D pci_memory; - } else { - pci_memory =3D NULL; - rom_memory =3D system_memory; - } - pc_guest_info_init(pcms); =20 if (pcmc->smbios_defaults) { @@ -212,14 +203,13 @@ static void pc_q35_init(MachineState *machine) /* create pci host bus */ phb =3D OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); =20 - if (pcmc->pci_enabled) { - pci_hole64_size =3D object_property_get_uint(phb, - PCI_HOST_PROP_PCI_HOLE6= 4_SIZE, - &error_abort); - } + pci_hole64_size =3D object_property_get_uint(phb, + PCI_HOST_PROP_PCI_HOLE64_SI= ZE, + &error_abort); =20 /* allocate ram and load rom/bios */ - pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); + memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); + pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); =20 object_property_add_child(OBJECT(machine), "q35", phb); object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, @@ -243,7 +233,7 @@ static void pc_q35_init(MachineState *machine) pcms->bus =3D host_bus; =20 /* irq lines */ - gsi_state =3D pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); + gsi_state =3D pc_gsi_create(&x86ms->gsi, true); =20 /* create ISA bus */ lpc =3D pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), @@ -286,9 +276,7 @@ static void pc_q35_init(MachineState *machine) pc_i8259_create(isa_bus, gsi_state->i8259_irq); } =20 - if (pcmc->pci_enabled) { - ioapic_init_gsi(gsi_state, "q35"); - } + ioapic_init_gsi(gsi_state, "q35"); =20 if (tcg_enabled()) { x86_register_ferr_irq(x86ms->gsi[13]); --=20 2.41.0