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Tsirkin" Subject: [RFC PATCH 4/7] hw/ide/sii3112: Configure IDE bus IRQs after realization Date: Fri, 9 Feb 2024 13:32:22 +0100 Message-ID: <20240209123226.32576-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240209123226.32576-1-philmd@linaro.org> References: <20240209123226.32576-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707482066684100007 We shouldn't call qdev_get_gpio_in() on unrealized devices. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Ideally we should rework the current IDE bus model to really use QOM and not globals. Left for later. --- hw/ide/sii3112.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 63dc4a0494..8b6e931f27 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -282,6 +282,15 @@ static void sii3112_pci_realize(PCIDevice *dev, Error = **errp) qdev_init_gpio_in(ds, sii3112_set_irq, 2); for (i =3D 0; i < 2; i++) { ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); + } +} + +static void sii3112_pci_wire(DeviceState *dev) +{ + PCIIDEState *s =3D PCI_IDE(dev); + DeviceState *ds =3D DEVICE(dev); + + for (unsigned i =3D 0; i < 2; i++) { ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i)); =20 bmdma_init(&s->bus[i], &s->bmdma[i], s); @@ -299,6 +308,7 @@ static void sii3112_pci_class_init(ObjectClass *klass, = void *data) pd->class_id =3D PCI_CLASS_STORAGE_RAID; pd->revision =3D 1; pd->realize =3D sii3112_pci_realize; + dc->wire =3D sii3112_pci_wire; dc->reset =3D sii3112_reset; dc->desc =3D "SiI3112A SATA controller"; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); --=20 2.41.0