From nobody Fri Oct 18 08:52:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1707479899; cv=none; d=zohomail.com; s=zohoarc; b=ntMMK9iAgFMqrS9KGGgeybZm3WwKiV8HfaOKnlPQ+3qotj1zTdGwN4yC67UMMt0ma9tqSlJfXRxsZNn8JkjGwtU9LFlEmYHE+0n/1d27T4Dd4pTL64e5D98zeAMFYGO2S3EERu0KGNdR4d8Z2FmlryjsW76pTIWDRxo1F9gQ7n4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1707479899; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7DQQGyD54a9+NK1Y31pcxxpnq6jGjDscpGocPa4Z9NE=; b=DoLnuhRKKCNJCqn0QaiPrx/mnLHmrih9+KWRKN59blwFdNgNxAv5cuqOob/f3Eu5TjSxUgQ3FD046BHN8dzNEBNt2Zt+WEWggJ9SxbC/LozLBtxvNc8Oo+YGh1EQj5wYjE8OfGeBXVsqQ6njyLXioC9qeOFa+FESf4ja5QOfSto= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1707479899142918.5411175557958; Fri, 9 Feb 2024 03:58:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rYPUu-0003WH-FS; Fri, 09 Feb 2024 06:56:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rYPUs-0003UH-K6 for qemu-devel@nongnu.org; Fri, 09 Feb 2024 06:56:46 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rYPUq-0002PW-TJ for qemu-devel@nongnu.org; Fri, 09 Feb 2024 06:56:46 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 9CC2562037; Fri, 9 Feb 2024 11:56:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A524C433C7; Fri, 9 Feb 2024 11:56:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707479803; bh=ubbnHP6CQJX6H46ApufgbUTl/GyRa/bvBIBXu8fglok=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lWl0fC8vR6X5eG6pH7xkNpXuXhEWMGNxNN0N0GkRNnIkDvZixdFDSNNX1C6uY8ib6 u/MA+dl4cQ/VksTeWlOZFs8HfdBqvCOIXIsNnqMM/Y60RlfBs8o2j/qOSyqTDcPfzh IppCwu5zrH9GqMgd45xlfBj8N73mPYBN+Y2E5pT/ekHorycSWPpd49n56GFsAdOndM HVR8CXnATEgZarJHHu5yuqRQ+fdEuUk08gh5K/9LECqG6H4AdsCmKQ/Caw2m8XFuE4 g/9l9SinprOsQIAkIBTm6QUfhFNCWGjkWAymLgyx9Q2FaLoKxW5lOPLR/HkfpmqpbS CxTdKAHj53IOw== From: deller@kernel.org To: qemu-devel@nongnu.org Cc: Sven Schnelle , Helge Deller , Richard Henderson , Jason Wang Subject: [PATCH v2 04/12] hw/pci-host/astro: Implement Hard Fail and Soft Fail mode Date: Fri, 9 Feb 2024 12:56:25 +0100 Message-ID: <20240209115633.55823-5-deller@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209115633.55823-1-deller@kernel.org> References: <20240209115633.55823-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.213, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1707479900537100003 Content-Type: text/plain; charset="utf-8" From: Helge Deller The Astro/Elroy chip can work in either Hard-Fail or Soft-Fail mode. Hard fail means the system bus will send an HPMC (=3Dcrash) to the processor, soft fail means the system bus will ignore timeouts of MMIO-reads or MMIO-writes and return -1ULL. The HF mode is controlled by a bit in the status register and is usually programmed by the OS. Return the corresponing values based on the current value of that bit. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- hw/pci-host/astro.c | 21 +++++++++++++++------ include/hw/pci-host/astro.h | 2 ++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 96d655f5fb..e3e589ceac 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -131,15 +131,21 @@ static MemTxResult elroy_chip_read_with_attrs(void *o= paque, hwaddr addr, if (s->iosapic_reg_select < ARRAY_SIZE(s->iosapic_reg)) { val =3D s->iosapic_reg[s->iosapic_reg_select]; } else { - val =3D 0; - ret =3D MEMTX_DECODE_ERROR; + goto check_hf; } } trace_iosapic_reg_read(s->iosapic_reg_select, size, val); break; default: - val =3D 0; - ret =3D MEMTX_DECODE_ERROR; + check_hf: + if (s->status_control & HF_ENABLE) { + val =3D 0; + ret =3D MEMTX_DECODE_ERROR; + } else { + /* return -1ULL if HardFail is disabled */ + val =3D ~0; + ret =3D MEMTX_OK; + } } trace_elroy_read(addr, size, val); =20 @@ -187,7 +193,7 @@ static MemTxResult elroy_chip_write_with_attrs(void *op= aque, hwaddr addr, if (s->iosapic_reg_select < ARRAY_SIZE(s->iosapic_reg)) { s->iosapic_reg[s->iosapic_reg_select] =3D val; } else { - return MEMTX_DECODE_ERROR; + goto check_hf; } break; case 0x0840: /* IOSAPIC_REG_EOI */ @@ -200,7 +206,10 @@ static MemTxResult elroy_chip_write_with_attrs(void *o= paque, hwaddr addr, } break; default: - return MEMTX_DECODE_ERROR; + check_hf: + if (s->status_control & HF_ENABLE) { + return MEMTX_DECODE_ERROR; + } } return MEMTX_OK; } diff --git a/include/hw/pci-host/astro.h b/include/hw/pci-host/astro.h index f63fd220f3..e2966917cd 100644 --- a/include/hw/pci-host/astro.h +++ b/include/hw/pci-host/astro.h @@ -27,6 +27,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ElroyState, ELROY_PCI_HOST_BRI= DGE) #define IOS_DIST_BASE_ADDR 0xfffee00000ULL #define IOS_DIST_BASE_SIZE 0x10000ULL =20 +#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */ + struct AstroState; =20 struct ElroyState { --=20 2.43.0