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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d20-20020a637354000000b005d3bae243bbsm1473623pgn.4.2024.02.09.02.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Feb 2024 02:58:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707476328; x=1708081128; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GkBieeUpGVnFbhuy6NCd8xFId+mBILOYnx7B36fkTzs=; b=jR8SYOsDR7mo1YI+yXfg5s1zBu3QyvZal3X0NWxSxlnMIhiPeKyOGNW0qrxHICRxx8 dEUMrYOGbJTZ9bg5E9kyahFHtQ1Zn7lI28Ij01ATbEl0XdzXwdnNTv/qezHCqLHQ8PMO MCxUanVruibQ4aVNN65dmLtDpbwYSQItibXurOraw+hGJgCWUn0QvCU0vmF7xvJsbYXS xhDREALMi2RCVRFL95Uph5t03BrqRIxMv/4AZ6at4JanAyIlNi85lWSDetdQnuQ6O3XC qFwDlCSglIx+Qgt2FKBIKnAYXJiBxMLPxV6fSXTd21EZfg2kw67XQx6BEu8e4tMB9vp6 CFkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707476328; x=1708081128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GkBieeUpGVnFbhuy6NCd8xFId+mBILOYnx7B36fkTzs=; b=LdRC+tt5YnUwjSi/Qj0k+oBD93+hhnxzv8P5hp5WY+KnMvaK0FKbGI7EKYVgfr2Fme OJ1pw+b/XyQ6tY3FDu2e0mHPlY1DonHHHt8DkZjVBcjrTN/oBQgsQwHcjwRpem23rQXA lKuSD27nz3pdt6eZ5l2vGmn8G9+uRvcqGNaian5+6Ae+jLADxc8xZBtd6WLshR4LvzrX FBLz+cjeefL75GOhoayV70/FwYqVBCTMC6iI3bSYnReLv3ERiDYW1YZu4b8XWDaSHxjs 4IskISMmY4zpswFjnaD3xvNdQyhUo2SvAYJb2904qF+ba2+vIQsv/2QBoHmQuhbxyWyX RALQ== X-Gm-Message-State: AOJu0YwF9fsGQ20BmOw35FSA/gveVwz7wfcvdI+97mYQ5NDwXahg64bp jq5/uyDloF4bOxXnwxjqO1oiHva80O9txPdjL8IZVRV7GjHFk50Qs+QjqWZtOIOPmg== X-Google-Smtp-Source: AGHT+IGuos9C8djF1W7gwjdn7iosTbRHpHtyfNe92jTuh2IxASD2jAEvq99q57OFMv0zUrHfNrjLMg== X-Received: by 2002:a05:6a21:31c8:b0:19e:b706:fe97 with SMTP id zb8-20020a056a2131c800b0019eb706fe97mr755009pzb.3.1707476328460; Fri, 09 Feb 2024 02:58:48 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCW5pczA6evAbm4XvxX325Q8eRCCwLQWeYaAuNAGGTzbLzZyOLgLdn92xCQvwttYyPq476g7d4xG0q51c6tCEjz+0SYXdCkPvcR+sJnIv2HzzkfRxkQ8BGSUUUU6O6W5yaeVZCyVrn/hl2KKShwj5zB7Lonr7qwpAcIp3oztDUnNO1g= From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Vladimir Isaev Subject: [PULL 07/61] target/riscv: move 'mmu' to riscv_cpu_properties[] Date: Fri, 9 Feb 2024 20:57:19 +1000 Message-ID: <20240209105813.3590056-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209105813.3590056-1-alistair.francis@wdc.com> References: <20240209105813.3590056-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1707476460066100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Commit 7f0bdfb5bfc ("target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()") already did some of the work by making some cpu_init() functions to explictly enable their own 'mmu' default. The generic CPUs didn't get update by that commit, so they are still relying on the defaults set by the 'mmu' option. But having 'mmu' and 'pmp' being default=3Dtrue will force CPUs that doesn't implement these options to set them to 'false' in their cpu_init(), which isn't ideal. We'll move 'mmu' to riscv_cpu_properties[] without any defaults, i.e. the default will be 'false'. Compensate it by manually setting 'mmu =3D true' to the generic CPUs that requires it. Implement a setter for it to forbid the 'mmu' setting to be changed for vendor CPUs. This will allow the option to exist for all CPUs and, at the same time, protect vendor CPUs from undesired changes: $ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,mmu=3Dtrue qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.mmu=3Dtrue: CPU 'sifive-e51' does not allow changing the value of 'mmu' Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev Message-ID: <20240105230546.265053-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 55 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1b11e9098b..3b5d6da736 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -437,6 +437,8 @@ static void riscv_max_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; RISCVMXL mlx =3D MXL_RV64; =20 + cpu->cfg.mmu =3D true; + #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; #endif @@ -451,7 +453,11 @@ static void riscv_max_cpu_init(Object *obj) #if defined(TARGET_RISCV64) static void rv64_base_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ @@ -569,13 +575,18 @@ static void rv64_veyron_v1_cpu_init(Object *obj) =20 static void rv128_base_cpu_init(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + if (qemu_tcg_mttcg_enabled()) { /* Missing 128-bit aligned atomics */ error_report("128-bit RISC-V currently does not work with Multi " "Threaded TCG. Please use: -accel tcg,thread=3Dsingle= "); exit(EXIT_FAILURE); } - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ @@ -609,7 +620,11 @@ static void rv64i_bare_cpu_init(Object *obj) #else static void rv32_base_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ @@ -1605,8 +1620,38 @@ static const PropertyInfo prop_pmu_mask =3D { .set =3D prop_pmu_mask_set, }; =20 +static void prop_mmu_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + + visit_type_bool(v, name, &value, errp); + + if (cpu->cfg.mmu !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, "mmu", errp); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.mmu =3D value; +} + +static void prop_mmu_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mmu; + + visit_type_bool(v, name, &value, errp); +} + +static const PropertyInfo prop_mmu =3D { + .name =3D "mmu", + .get =3D prop_mmu_get, + .set =3D prop_mmu_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), @@ -1695,6 +1740,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "pmu-mask", .info =3D &prop_pmu_mask}, {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 + {.name =3D "mmu", .info =3D &prop_mmu}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif --=20 2.43.0