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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d20-20020a637354000000b005d3bae243bbsm1473623pgn.4.2024.02.09.03.01.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Feb 2024 03:01:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707476501; x=1708081301; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JrmiXcpe1bZMLQTSTIo9vxkWrCjtZwGRKfh570INs5g=; b=lQOHlUBQMP12DTujDulgV3kze3fpQk9+KMbnyQjBExraLaUbZ31ebvw/vf7RUm/yxn LgJqD8XAq8xIMoD/9yLoK3qJCncWqIbRkH4iyexqatJM2QScbl0lxRuTkuxN2UzGtpkO F73utTlJ1gKQtJpUi4bhDqlgMhPBwtzWL5KvhF9obkmkcLNeFbL82/iYSFZu/j/65Qh/ A0KxkVsUj6Qh+vKPhKUcy9pPpoPn+Ii41iHaqGQnBCbXkXu1qSkc7e4KCOIChbfhiS9q Ka0Bjcg8HYjgCxmPMEIvO22hU+jDXvja5wn0vbp/HeoeOJmGTYRCFDaQ+NZrEz2TtpJ2 l27A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707476501; x=1708081301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JrmiXcpe1bZMLQTSTIo9vxkWrCjtZwGRKfh570INs5g=; b=UmeGP1PUEh99lw9UVTKxbeRZbwsT4p1lqeE8OqJ5uC7AerpUnfbSLrcPLuJNKkGvFm ZHvNTngu6KcsX34n42zH1s8h6LkbGQito2QjT22gX+Aof86SmjzzWuBOy7ANw2tuhRSz p5J4oQeQJ5buV6pjviTEbw5I3BhhIaGc07mVQX3yU7i1d+HDzDawMB7qZBUUp/2rBhIo JEiYXDkAJ9/jHm3FmY+EX+R046wMqB+nTyCrjrk5AaUh0SEOwBg/dlDBVq1Ut7+Y6i8y qIF9h3nroj/haCXUUVn1eFwfFV+jTROH0SgHRsAHnSxRKu806bXkBlez/G6bEfNpPzcW zSig== X-Gm-Message-State: AOJu0Ywadb63pg8cxwW3l2TUkd1jTFsHkv0eSuHI/lIYwGv/0SfOEmWk uKg3DKF7lBtC1ULc3krw7AYfaWHy59Cqns8W4MBaEBolMBDl4TocfGbhWeGIVWFnEA== X-Google-Smtp-Source: AGHT+IEoym8TtjJE0CbCJkSLq50VB7hI5mJ1Z37RQnTZ2i9gYKW9L1iyUQl2oLSdRYpmdVZyMGbsyA== X-Received: by 2002:a05:6a00:3a97:b0:6e0:5281:e0d1 with SMTP id fk23-20020a056a003a9700b006e05281e0d1mr1288582pfb.1.1707476501436; Fri, 09 Feb 2024 03:01:41 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXoVICyZ5QsGp5jjM725+Sc0E1WKd8J7qHbLvbELVws65DEHtEYGAcWM0fur8R+evFFYVSDDdokzFFepzd+U4m5E8jY2JxMBuRuAvBHVKGbV7Wa8nmGuWAeEB95zh8uQRj+Uq8= From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL 60/61] target/riscv/cpu.c: add riscv_bare_cpu_init() Date: Fri, 9 Feb 2024 20:58:12 +1000 Message-ID: <20240209105813.3590056-61-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209105813.3590056-1-alistair.francis@wdc.com> References: <20240209105813.3590056-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=alistair23@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1707476857869100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Next patch will add more bare CPUs. Their cpu_init() functions would be glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a riscv_cpu_set_misa() call. Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ to avoid this code repetition. While we're at it, add a better explanation on why we're disabling the timing extensions for bare CPUs. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240122123348.973288-2-dbarboza@ventanamicro.com> [ Changes by AF: - Rebase on latest changes ] Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b5878c603..08fc24c3f4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -605,22 +605,6 @@ static void rv64i_bare_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; riscv_cpu_set_misa_ext(env, RVI); - - /* Remove the defaults from the parent class */ - RISCV_CPU(obj)->cfg.ext_zicntr =3D false; - RISCV_CPU(obj)->cfg.ext_zihpm =3D false; - - /* Set to QEMU's first supported priv version */ - env->priv_ver =3D PRIV_VERSION_1_10_0; - - /* - * Support all available satp_mode settings. The default - * value will be set to MBARE if the user doesn't set - * satp_mode manually (see set_satp_mode_default()). - */ -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); -#endif } #else static void rv32_base_cpu_init(Object *obj) @@ -1329,6 +1313,34 @@ static void riscv_cpu_init(Object *obj) cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 +static void riscv_bare_cpu_init(Object *obj) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + + /* + * Bare CPUs do not inherit the timer and performance + * counters from the parent class (see riscv_cpu_init() + * for info on why the parent enables them). + * + * Users have to explicitly enable these counters for + * bare CPUs. + */ + cpu->cfg.ext_zicntr =3D false; + cpu->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + cpu->env.priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV64); +#endif +} + typedef struct misa_ext_info { const char *name; const char *description; @@ -2505,6 +2517,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_BARE_CPU, .parent =3D TYPE_RISCV_CPU, + .instance_init =3D riscv_bare_cpu_init, .abstract =3D true, }, #if defined(TARGET_RISCV32) --=20 2.43.0