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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d20-20020a637354000000b005d3bae243bbsm1473623pgn.4.2024.02.09.03.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Feb 2024 03:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707476480; x=1708081280; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PFfabkqZ7+KZbRfwTJjM37aj+onUUvLrbV1BgbFXOZk=; b=Qw+oTd7egFkyQ/xUSnuzEwY8Gf9oh0SsDHXl+VqFyYPm1abgk1JPQ+dpuMdu0W69qi 7F/OUytVlBi1ctRGNEnpi2y68RYc7L6oH7rLFkUDjeOMyc4VPOTyaEz9gv47rym+4O3P ue+9M6ntHaDaKTtpfrWND7NmFaK0wFB6C36vA1CAjVyC8JT3t+1xwmaHZplJDsa/pqCT ZH9LELn2+GFWDwBbp3T28v3PnyOTOyITO8Y1KlH9pBCrhbkK27yOQV1hdu7CI1Yac/+W 3YJk5kCdCCA7vAsKaauv/PyEfZhHFVSYPfVbq8s3r8BWZAby2cvN2HLW8aBgShm03epD ioPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707476480; x=1708081280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PFfabkqZ7+KZbRfwTJjM37aj+onUUvLrbV1BgbFXOZk=; b=VYDW+W+sN8cYxZLQsUWOlsW0mq7qfy3mf/txvSW+KaWRX76tkJgB6PViNXJZpDqfg2 CETmEWJEEOM9wEiLcbZMPqAFn3HhsKmV2S2Lr6raiJKqIOD/in2M0M7ht+ASFxsZspqh 4OsqMvsRbI2tJACpBM07Zv+fdlGCZVd8cZe5GDvORZjGUpNtHG3UNPopEB+Lrh2xuQ0l 5K038OOOhg0Qa0SnpchQNwdgQVgb4hJktq5mESiHQoiVViTgDHowJZTIIhA8YWxI6mI3 XESrNN6Wy23ioy5+oDYCO8X4fXEcY+9IQ0+UfTvd+lXDW21wwgBtGhitfbD1c0TRSqru 3Big== X-Gm-Message-State: AOJu0YztLCMDwidolVksCjBAOWlR7pz3nb1TA3bWy5UWq/1hqGeWpnVi TuoniolWJTe3gD2XovKNd+axYG65XWuRpfCaz7r2yQ7VEcqLUBuIAJ+zH1UrMkBWMA== X-Google-Smtp-Source: AGHT+IFThFb+lQJki51H4Ge6C95UaiWODlmhSzulL28urTvO38HivEEnyoYdGuzxC33bKxBru6jGCA== X-Received: by 2002:a05:6e02:d03:b0:363:c181:ab8b with SMTP id g3-20020a056e020d0300b00363c181ab8bmr1514592ilj.5.1707476478274; Fri, 09 Feb 2024 03:01:18 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCW0O4k65EE+1FatG8ycXJuwD1VowPdz11odf9NEagFmARgxGpbCD21Mfmk/8VuyNr+8dBUF6AZLLjHvS2RnD/fag68hFDfq42RRgREGy37wPSLFPPXjwRe/jwM4Ado2DyXOTTGBVe9xcvIFC/xEo0SIql2fdlkva82oeuSNoFf1xuF/RomHPb5ItBRg3sGJFLR88eXdwZwFMw== From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Conor Dooley , Andrew Jones , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 53/61] target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS Date: Fri, 9 Feb 2024 20:58:05 +1000 Message-ID: <20240209105813.3590056-54-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209105813.3590056-1-alistair.francis@wdc.com> References: <20240209105813.3590056-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d36; envelope-from=alistair23@gmail.com; helo=mail-io1-xd36.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1707476922106100003 Content-Type: text/plain; charset="utf-8" From: Conor Dooley A cpu may not have the same xlen as the compile time target, and misa_mxl_max is the source of truth for what the hart supports. The conversion from misa_mxl_max to xlen already has one user, so introduce a helper and use that to populate the isa string. Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@= orel/ Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones Reviewed-by: Daniel Henrique Barboza Message-ID: <20240124-swear-monthly-56c281f809a6@spud> [ Changes by AF: - Convert to use RISCVCPUClass *mcc ] Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 10 +++++++++- target/riscv/gdbstub.c | 2 +- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 285a247368..9bc14056fa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -511,6 +511,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); +int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(const char *optname); =20 #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 84902be070..7fc45660d7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -308,6 +308,11 @@ void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32= _t ext) env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 +int riscv_cpu_max_xlen(RISCVCPUClass *mcc) +{ + return 16 << mcc->misa_mxl_max; +} + #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -2357,10 +2362,13 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, cha= r **isa_str, =20 char *riscv_isa_string(RISCVCPU *cpu) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); int i; const size_t maxlen =3D sizeof("rv128") + sizeof(riscv_single_letter_e= xts); char *isa_str =3D g_new(char, maxlen); - char *p =3D isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BI= TS); + int xlen =3D riscv_cpu_max_xlen(mcc); + char *p =3D isa_str + snprintf(isa_str, maxlen, "rv%d", xlen); + for (i =3D 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { *p++ =3D qemu_tolower(riscv_single_letter_exts[i]); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 0ae0c47df1..ca9b71f7bb 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -221,7 +221,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int = base_reg) CPURISCVState *env =3D &cpu->env; GString *s =3D g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize =3D 16 << mcc->misa_mxl_max; + int bitsize =3D riscv_cpu_max_xlen(mcc); int i; =20 #if !defined(CONFIG_USER_ONLY) --=20 2.43.0