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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d20-20020a637354000000b005d3bae243bbsm1473623pgn.4.2024.02.09.03.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Feb 2024 03:00:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707476410; x=1708081210; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/PW4HgfpqFA/T+gchjLsJDFYxSNqSSKYfz4pvfD/U1k=; b=bhLp3JK855VJltqDMbjPXOJL9P4zmAXh1mVXhu/yd74kx+keWsCFfy5SIUooHgMzG+ EImeg+MGrB7zpxD5n/vXcIWOFvXEhWe5P0viMH6O6yc7UVFX11HqXeFOUkd3cV/iCbO4 F/z5mCAQDAkpUi0szOwgEZkz9HUJEIRcaTfc6TABwDFmRgKL3s1+o4VoYFwFvRq/fzpj coZF5UN6M/gNLXc/GxMqV2BQZ8XCgMuj4iPzyu2fZS4vXsHpNHVgrWnL1h9H75SL4Zq1 8dxQhZVHpGxfJc+vkUZ8rhR2GFdLtBezeDJMoqpDzvcDsydNkKPJFXFOlkMJI+qcNX36 yG0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707476410; x=1708081210; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/PW4HgfpqFA/T+gchjLsJDFYxSNqSSKYfz4pvfD/U1k=; b=FXt+NynF1pztgmCXGZsUJLt4di2ynUyRhn7+wPtZs9Y/ph9QM0cF+Tvn0lwYh6Bk73 k31TaqeGwChhSCLw7srMQ8GpNUY7L8YuJXs2Evms83snY4bBXhIfFPCo8T2Bnd+mgNAt JEsNQ/AdVZwC9gACk8mTJjF43sN0IyS8JMzy5sVxy3P5KsEtobJ2jGvu+2yIxLLVN24W FB81TA8n9D6COcKGS7aSLSm0DPPYtOeAgKgeYzuk8MoSsxzksr/HLo8Mk+9QErZi1xRI se1MG31T/2ozmcmYUE1/k/3XEG6kLruS829fwqZ/VhcLGmkIrdwahRM8WGUIRkp+Ah28 gQNw== X-Gm-Message-State: AOJu0YwFNi+AyTm05W9YcKS9KGKmTt+gYtj9IV55Myj0LQvwqhnUgMFX Buq/SfHTuFrMi3Y5n0SkPrrPzKXLiEoc+JCqhlqNpJkMy+Iwb+0iV1x4jszOspLx8w== X-Google-Smtp-Source: AGHT+IHvb83LIaVPZRDQ6M7ufLcJ4RbsrM5IuULboI+O3eKulimyKbxDsh8WlUj+Njf1wRYtCnYjHA== X-Received: by 2002:a05:6830:3b86:b0:6e1:1501:58a5 with SMTP id dm6-20020a0568303b8600b006e1150158a5mr1077380otb.13.1707476410481; Fri, 09 Feb 2024 03:00:10 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCUTGhUwF4A1yvTerOhSwlhlV0VB6J+9NSbgDICkHEEm9uYIG5sIT6MrkybrVIi3wItKObWpJFuJ8v/FNWfbl546ePyhQhfgVBRJhXIen0uYD4QAurzg8AN3TigT9PAXx0vAcqw= From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL 32/61] target/riscv: change vext_get_vlmax() arguments Date: Fri, 9 Feb 2024 20:57:44 +1000 Message-ID: <20240209105813.3590056-33-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209105813.3590056-1-alistair.francis@wdc.com> References: <20240209105813.3590056-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=alistair23@gmail.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1707476934189100008 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We'll re-use the logic froim vext_get_vlmax() in 2 other occurrences in the next patch, but first we need to make it independent of both 'cpu' and 'vtype'. To do that, add 'vlenb', 'vsew' and 'lmul' as parameters instead. Adapt the two existing callers. In cpu_get_tb_cpu_state(), rename 'sew' to 'vsew' to be less ambiguous about what we're encoding into *pflags. In HELPER(vsetvl) the following changes were made: - add a 'vsew' var to store vsew. Use it in the shift to get 'sew'; - the existing 'lmul' var was renamed to 'vlmul'; - add a new 'lmul' var to store 'lmul' encoded like DisasContext:lmul. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240122161107.26737-12-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 7 +++---- target/riscv/cpu_helper.c | 11 +++++++---- target/riscv/vector_helper.c | 16 ++++++++++------ 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1c5a363e4b..07f797406c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -688,11 +688,10 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *e= nv) * =3D 256 >> 7 * =3D 2 */ -static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) +static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, + int8_t lmul) { - uint8_t vsew =3D FIELD_EX64(vtype, VTYPE, VSEW); - int8_t lmul =3D sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); - uint32_t vlen =3D cpu->cfg.vlenb << 3; + uint32_t vlen =3D vlenb << 3; =20 /* * We need to use 'vlen' instead of 'vlenb' to diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b6b23b7d03..d462d95ee1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -81,13 +81,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue * only when maxsz >=3D 8 bytes. */ - uint32_t vlmax =3D vext_get_vlmax(cpu, env->vtype); - uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); - uint32_t maxsz =3D vlmax << sew; + + /* lmul encoded as in DisasContext::lmul */ + int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); + uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); + uint32_t maxsz =3D vlmax << vsew; bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && (maxsz >=3D 8); flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8ee7717162..84cec73eb2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -35,16 +35,18 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_= ulong s1, { int vlmax, vl; RISCVCPU *cpu =3D env_archcpu(env); - uint64_t lmul =3D FIELD_EX64(s2, VTYPE, VLMUL); - uint16_t sew =3D 8 << FIELD_EX64(s2, VTYPE, VSEW); + uint64_t vlmul =3D FIELD_EX64(s2, VTYPE, VLMUL); + uint8_t vsew =3D FIELD_EX64(s2, VTYPE, VSEW); + uint16_t sew =3D 8 << vsew; uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); int xlen =3D riscv_cpu_xlen(env); bool vill =3D (s2 >> (xlen - 1)) & 0x1; target_ulong reserved =3D s2 & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, xlen - 1 - R_VTYPE_RESERVED_SH= IFT); + int8_t lmul; =20 - if (lmul & 4) { + if (vlmul & 4) { /* * Fractional LMUL, check: * @@ -53,8 +55,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ul= ong s1, * (vlenb << 3) >> (8 - lmul) >=3D sew * vlenb >> (8 - 3 - lmul) >=3D sew */ - if (lmul =3D=3D 4 || - cpu->cfg.vlenb >> (8 - 3 - lmul) < sew) { + if (vlmul =3D=3D 4 || + cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) { vill =3D true; } } @@ -68,7 +70,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ul= ong s1, return 0; } =20 - vlmax =3D vext_get_vlmax(cpu, s2); + /* lmul encoded as in DisasContext::lmul */ + lmul =3D sextract32(FIELD_EX64(s2, VTYPE, VLMUL), 0, 3); + vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); if (s1 <=3D vlmax) { vl =3D s1; } else { --=20 2.43.0