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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d20-20020a637354000000b005d3bae243bbsm1473623pgn.4.2024.02.09.02.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Feb 2024 02:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707476371; x=1708081171; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OOf62pxwajXdelK5+pHplTSF3EihEn5ntNS6KqedNMU=; b=NwQGJKAgHvs44LanShO7SMoJWkZOMZNmZ75zHm04L4qa6dYKC+p9cq6VUj7RxNbS2N N4Zx7uH2fnOyZZwJeSgzKiyZuDyAtc490wWiRc2nnodpBwnoQHfZzi0q07GkLPTOQHLj cGbCFk1DBtRGYc9uwsBnysTveiZB0TyEcP0SRNOsmu9VnUxNY07h8qO/VBz58g6J8gFQ P2mqciWmsghC62mW38BmqwXECnaiShu4PSKadZaICYrFHdVl89JAuZp6t1brnOSMgfSi oOfLNLmerUMvKvjSLQ7M0KK/zTLb2+po2JG7pq828wndxG3ofnx9O8ryhw1S33b4bBqT rYIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707476371; x=1708081171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OOf62pxwajXdelK5+pHplTSF3EihEn5ntNS6KqedNMU=; b=SWDbpomsZ7t0hRUg2Pugs+gPRpHQIzB4zNnx+YtJIYzZn45ABFOocWsCt5IZ6mRr+0 u7MnsA8Q+C9OUVGajuUyfULJB3zcSGVRIVx/rE3+cxvlxpTtNHCQRaWCx3jDB7BktMm9 y50tk38bXiZ4T5boR8DU3AXLQe2xwK/dIpJf35U93hz1S5roZr0tEpZjvrkux1gogwGs ItWDhnNDB3OkXZ4w51EF+Ap0nvuQhdDzTdBAK+KtkDqFGi/pi5Pbyuti1RhCs4TGTJEc rjqbS6NWSQVxLOAGdXXitbbggbC0D01YUyIOTPv+6JeviYjF2g67FIlStkMNhfCsAkKK lW+A== X-Gm-Message-State: AOJu0YyEhcIO3RWlZ3KD8tbAWy9nx+FKboRQGY1qQo5G98vkcAEB7AQV CRfF+2pOUbtOtKtx3NSC9ftlLM9VzQnl1gnSt42iFMiRw3lnLVkgmBz0VEcL+TAvsA== X-Google-Smtp-Source: AGHT+IFeKFGBwGVHc3lORk/PQcxC1UVUb7PRPSj/5/HSEl+XulLXwLiJhKonioqDLQxAKY5Cf570vA== X-Received: by 2002:a05:6870:c1d3:b0:219:ab97:4a5b with SMTP id i19-20020a056870c1d300b00219ab974a5bmr1192944oad.57.1707476371484; Fri, 09 Feb 2024 02:59:31 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWR4ha7di0IHt4APjtaFI2uB9c+MnoDViZvcw4swe0M1sU+b7g6mS1V6lzPUBQAkNKusw65BLAKsoVoEDhAgOrUe4NB3krOvPDTgQj2VtsXPjLjjuL3SZ8OFBBrI5fnqo+sGxaaNypyj1tdBnQkY/bj3/lUI/axqwgZFwLKPshgX3E= From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Vladimir Isaev Subject: [PULL 20/61] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] Date: Fri, 9 Feb 2024 20:57:32 +1000 Message-ID: <20240209105813.3590056-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209105813.3590056-1-alistair.francis@wdc.com> References: <20240209105813.3590056-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=alistair23@gmail.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1707476417843100011 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev tested-by tags added, rebased with Alistair's riscv-to-apply.next. Message-ID: <20240112140201.127083-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 110 +++++++++++++++++++++++---------------------- 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a6524f01f..cce75aec3e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2055,6 +2055,62 @@ static const PropertyInfo prop_mimpid =3D { .set =3D prop_mimpid_set, }; =20 +static void prop_marchid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.marchid; + uint64_t value, invalid_val; + uint32_t mxlen =3D 0; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: + mxlen =3D 32; + break; + case MXL_RV64: + case MXL_RV128: + mxlen =3D 64; + break; + default: + g_assert_not_reached(); + } + + invalid_val =3D 1LL << (mxlen - 1); + + if (value =3D=3D invalid_val) { + error_setg(errp, "Unable to set marchid with MSB (%u) bit set " + "and the remaining bits zero", mxlen); + return; + } + + cpu->cfg.marchid =3D value; +} + +static void prop_marchid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; + + visit_type_uint64(v, name, &value, errp); +} + +static const PropertyInfo prop_marchid =3D { + .name =3D "marchid", + .get =3D prop_marchid_get, + .set =3D prop_marchid_set, +}; + /* * RVA22U64 defines some 'named features' or 'synthetic extensions' * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa @@ -2143,6 +2199,7 @@ static Property riscv_cpu_properties[] =3D { =20 {.name =3D "mvendorid", .info =3D &prop_mvendorid}, {.name =3D "mimpid", .info =3D &prop_mimpid}, + {.name =3D "marchid", .info =3D &prop_marchid}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -2224,56 +2281,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint64_t prev_val =3D cpu->cfg.marchid; - uint64_t value, invalid_val; - uint32_t mxlen =3D 0; - - if (!visit_type_uint64(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", - object_get_typename(obj), prev_val); - return; - } - - switch (riscv_cpu_mxl(&cpu->env)) { - case MXL_RV32: - mxlen =3D 32; - break; - case MXL_RV64: - case MXL_RV128: - mxlen =3D 64; - break; - default: - g_assert_not_reached(); - } - - invalid_val =3D 1LL << (mxlen - 1); - - if (value =3D=3D invalid_val) { - error_setg(errp, "Unable to set marchid with MSB (%u) bit set " - "and the remaining bits zero", mxlen); - return; - } - - cpu->cfg.marchid =3D value; -} - -static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; - - visit_type_uint64(v, name, &value, errp); -} - static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -2305,9 +2312,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, - cpu_set_marchid, NULL, NULL); - device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.43.0