From nobody Mon Sep 16 19:39:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1707476555; cv=none; d=zohomail.com; s=zohoarc; b=D67u2oq0yhhdZMzJR/S1JvLLO1oPy2BKSYzc1U0AyQgDTWl+nVTeDv0rAQWv0unSRV4koCD2ZPbWDsmqzzgNAYXSiUrj6O80ZIB9UJ8s3jxOjF7qRnkH+Mrj602gFFnHfYW7oUbkumQgzxr+8nrK8rMHSrvnsg5+9vJrZwySlHA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1707476555; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kvSrjBWPr8+krUa2FgRCezO4cbWcCwvAHM73Bgb9B9g=; b=RNGTjtCsld+GJBbpEx5LGDuR7WY1r/n3EuPTO30RE8kdt9lbQAHcKoiPvLmi67JxNIP2EQuV3vwxUfqrQFtpbOeV/gJ3bXNHUSeJX8VMRTuYbodgafSUqTq38oKLRTzkD0KGqGUMolQ8stpfD0f/3GMDmhiKj88E3+DyU8IQ4sk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1707476555222774.8567377217672; Fri, 9 Feb 2024 03:02:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rYOb2-0000LW-4r; Fri, 09 Feb 2024 05:59:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rYOaz-0000B3-CV for qemu-devel@nongnu.org; Fri, 09 Feb 2024 05:59:01 -0500 Received: from mail-oo1-xc2e.google.com ([2607:f8b0:4864:20::c2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rYOax-0000Es-R8 for qemu-devel@nongnu.org; Fri, 09 Feb 2024 05:59:01 -0500 Received: by mail-oo1-xc2e.google.com with SMTP id 006d021491bc7-59cf4872e1dso352718eaf.1 for ; Fri, 09 Feb 2024 02:58:59 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d20-20020a637354000000b005d3bae243bbsm1473623pgn.4.2024.02.09.02.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Feb 2024 02:58:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707476338; x=1708081138; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kvSrjBWPr8+krUa2FgRCezO4cbWcCwvAHM73Bgb9B9g=; b=CIGopDsrmLxkuvISgrdx/nCo18yIoYToXezs8eZtEbm9ecztMncifmXwYETAln7NS9 1OV0Lcviso4anfWm76TLj8KiUbBPJxfB8sEZlXShKyvo5muYDw1TNdPnSg5RUJwHmMdP lT2CY1sOlpkKZ3E5R/eMQN7nfw2MA5RVe9ktJybNs2KHge1CwQmD4Vpn6CIBwIGv0RNl wVH0S4a9EPckLD8Bh++z8c5ZfzgKPYeWM2VaAIuV8/qFyKWXS5x3hGc/jJH0lQoOb/Nh DGNyoTQ1vxJeH+rI4af7I8HisTxoF5jCjLcfK66kARHQ+HNtYQRYqAT2+kPQoOIS6e0U 8qmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707476338; x=1708081138; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kvSrjBWPr8+krUa2FgRCezO4cbWcCwvAHM73Bgb9B9g=; b=tHqKXvxGaGGhYkZUNaA3sdg7PddgfpB0ZP+M8J4LyzNN7+wyT0JrmkSbXMxZdVyPfw XARhB6cImqWhCJhspR876wTLs4v2mWb312oWrj9C5eCTpJ7eMYpKXvIuu2106OhcbVyl 9ofICQkQRyTkVvy6uIOsiH7brtLA4t6dVHkoCX6lunEanEbexOKKcXCdk3UGu0BuEG+K dDDZ6gtRt+yGbBZtKuYkc+AUfVLLDdpWJzvxJOMaWf9DhmpZjPMhZDEok5RsF3RlvfcY WvCozA//muaFmPNif1RMTVrPauFomIlQk0WDEvcrEx3xoRxfStrmrKznXenWX6f+f4AS 9LMw== X-Gm-Message-State: AOJu0Yw2ykIGbgwVQLv8bOOxF0shIQ7rsieAGxqbft7/SXA39vfzCYye E+xAbMTrPcwZ58uf6k2ILfPooxupaj9oCxEc4j3AutWHQtuH6VhSJJCJgYUfqed+ag== X-Google-Smtp-Source: AGHT+IEQUrqhsGrsSptKQ2FHg9JE6MxjFYkXdeY+VwgeP8wEVCDOe/Ha0HhPai0H2tU3iJViFd8eEA== X-Received: by 2002:a05:6358:c83:b0:178:98c8:9d76 with SMTP id o3-20020a0563580c8300b0017898c89d76mr1142132rwj.26.1707476338521; Fri, 09 Feb 2024 02:58:58 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXJEmj3gtbFSdyFVRor8/CYQ1sDMuEqGcHe6DOrdz/RR3Zqu1rppf3iFHRJ1kVQcFzXLSNRvfq028kZsLbW++wzr7qUCa4JgoeqYKgGcHO4ZPQDYCftQP6GtFYxSHbbILS/vM4C2H9MSdHOVB2Kla3J/Z8/oIYwZ1fMZXYdRtHTgMY= From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Vladimir Isaev Subject: [PULL 10/61] target/riscv: rework 'vext_spec' Date: Fri, 9 Feb 2024 20:57:22 +1000 Message-ID: <20240209105813.3590056-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209105813.3590056-1-alistair.francis@wdc.com> References: <20240209105813.3590056-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1707476556497100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The same rework did in 'priv_spec' is done for 'vext_spec'. This time is simpler, since we only accept one value ("v1.0") and we'll always have env->vext_ver set to VEXT_VERSION_1_00_0, thus we don't need helpers to convert string to 'vext_ver' back and forth like we needed for 'priv_spec'. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev Message-ID: <20240105230546.265053-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_cfg.h | 1 - target/riscv/cpu.c | 35 +++++++++++++++++++++++++++++++++-- target/riscv/tcg/tcg-cpu.c | 15 --------------- 4 files changed, 34 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index afecbbb0c1..2a5e67c141 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -106,6 +106,7 @@ enum { }; =20 #define VEXT_VERSION_1_00_0 0x00010000 +#define VEXT_VER_1_00_0_STR "v1.0" =20 enum { TRANSLATE_SUCCESS, diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 68965743b6..fea14c275f 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -139,7 +139,6 @@ struct RISCVCPUConfig { bool ext_XVentanaCondOps; =20 uint32_t pmu_mask; - char *vext_spec; uint16_t vlen; uint16_t elen; uint16_t cbom_blocksize; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8c8374a11..1a7a2f1d64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1317,6 +1317,7 @@ static void riscv_cpu_init(Object *obj) =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); + cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 typedef struct misa_ext_info { @@ -1756,9 +1757,38 @@ static const PropertyInfo prop_priv_spec =3D { .set =3D prop_priv_spec_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), +static void prop_vext_spec_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + g_autofree char *value =3D NULL; =20 + visit_type_str(v, name, &value, errp); + + if (g_strcmp0(value, VEXT_VER_1_00_0_STR) !=3D 0) { + error_setg(errp, "Unsupported vector spec version '%s'", value); + return; + } + + cpu_option_add_user_setting(name, VEXT_VERSION_1_00_0); + cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; +} + +static void prop_vext_spec_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const char *value =3D VEXT_VER_1_00_0_STR; + + visit_type_str(v, name, (char **)&value, errp); +} + +static const PropertyInfo prop_vext_spec =3D { + .name =3D "vext_spec", + .get =3D prop_vext_spec_get, + .set =3D prop_vext_spec_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 @@ -1846,6 +1876,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "pmp", .info =3D &prop_pmp}, =20 {.name =3D "priv_spec", .info =3D &prop_priv_spec}, + {.name =3D "vext_spec", .info =3D &prop_vext_spec}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fdcbea4b23..9820612f36 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -321,21 +321,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, "in the range [8, 64]"); return; } - - if (cfg->vext_spec) { - if (!g_strcmp0(cfg->vext_spec, "v1.0")) { - env->vext_ver =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, "Unsupported vector spec version '%s'", - cfg->vext_spec); - return; - } - } else if (env->vext_ver =3D=3D 0) { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - - env->vext_ver =3D VEXT_VERSION_1_00_0; - } } =20 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) --=20 2.43.0