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Fri, 09 Feb 2024 01:06:19 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXba0bkHEBVCjQNvRx1q2Nyy1RCIXN2+qbY3wMawd5vW8KefPyxQZtoRKCwm2YTNMjWaL6UQGqa60SkXsCL1UI7lKrpUt6B5I/bPdKjHoEAKz07aIOK+SQ7NlXVRj1kJaPVgDjnmyFmkJmjkPXYtzolEM14QXS5SCl+pMQRdUIw+3gr8G8k2nRRaqb4AseREJ1qrDc7JF+11uUm0YuetxxQQ4MujXLJeaLYhBqD27SBz+V+iHGMNXdrDt+H0kLdQdesGAeJzb4PfsRNLf9H1jK6Q1MIF6o7z9s3zacfNEw8sB9egUiGmiru6EbMKqI3vJWTCdQQaj/S7/Nk9HEQDvmqbWLnq1I= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Aurelien Jarno , Laurent Vivier , Jiaxun Yang , Paolo Bonzini , Peter Maydell , Huacai Chen , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 11/11] target/mips: Remove I6500 CPU definition Date: Fri, 9 Feb 2024 10:05:12 +0100 Message-ID: <20240209090513.9401-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240209090513.9401-1-philmd@linaro.org> References: <20240209090513.9401-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469645270100003 I6500 support is incomplete as it lacks SAAR (Special Address Access Register) and DSPRAM (Data Scratch Pad RAM) features. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- docs/about/removed-features.rst | 5 +++++ tests/qtest/machine-none-test.c | 2 +- target/mips/cpu-defs.c.inc | 40 --------------------------------- 3 files changed, 6 insertions(+), 41 deletions(-) diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index 54081a6c19..d61b4c92dd 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -727,6 +727,11 @@ x86 ``Icelake-Client`` CPU (removed in 7.1) There isn't ever Icelake Client CPU, it is some wrong and imaginary one. Use ``Icelake-Server`` instead. =20 +MIPS I6500 CPU (removed in 9.0) +''''''''''''''''''''''''''''''' + +The I6500 support was never fully contributed. + System accelerators ------------------- =20 diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-tes= t.c index 31cc0bfb01..b653a0dd5c 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -37,7 +37,7 @@ static struct arch2cpu cpus_map[] =3D { { "mips", "4Kc" }, { "mipsel", "I7200" }, { "mips64", "20Kc" }, - { "mips64el", "I6500" }, + { "mips64el", "I6400" }, { "nios2", "FIXME" }, { "or1k", "or1200" }, { "ppc", "604" }, diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fbf787d8ce..ce2c01cbfa 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -778,46 +778,6 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS64R6, .mmu_type =3D MMU_TYPE_R4000, }, - { - .name =3D "I6500", - .CP0_PRid =3D 0x1B000, - .CP0_Config0 =3D MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_= AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU= ) | - (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA)= | - (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA)= | - (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 =3D MIPS_CONFIG2, - .CP0_Config3 =3D MIPS_CONFIG3 | (1U << CP0C3_M) | - (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | - (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULR= I) | - (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_V= Int), - .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | - (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), - .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP)= | - (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_G= I), - .CP0_Config5_rw_bitmask =3D (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI)= | - (1 << CP0C5_FRE) | (1 << CP0C5_UFE), - .CP0_LLAddr_rw_bitmask =3D 0, - .CP0_LLAddr_shift =3D 0, - .SYNCI_Step =3D 64, - .CCRes =3D 2, - .CP0_Status_rw_bitmask =3D 0x30D8FFFF, - .CP0_PageGrain =3D (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | - (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask =3D (1 << CP0PG_ELPA), - .CP0_EBaseWG_rw_bitmask =3D (1 << CP0EBase_WG), - .CP1_fcr0 =3D (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_= F64) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV= ), - .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .CP1_fcr31_rw_bitmask =3D 0x0103FFFF, - .MSAIR =3D 0x03 << MSAIR_ProcID, - .SEGBITS =3D 48, - .PABITS =3D 48, - .insn_flags =3D CPU_MIPS64R6, - .mmu_type =3D MMU_TYPE_R4000, - }, { .name =3D "Loongson-2E", .CP0_PRid =3D 0x6302, --=20 2.41.0