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Fri, 09 Feb 2024 01:05:21 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWfVt9ioVBAQp7E/L5r8u8qvyBkurRg1WzvG2XfIAeb+MmOpkhZZPmuCFKsjjN0unzqv466T5ns3qrAjX0w2Y9tMhoGDlo/WjlWPUj9uU5F/Sha1/PaoJDEhLW4Mzy9SNOIj0ewnWwTz15/EfHAgajkfXRY9CFw8meQDyBj3/Qsi78y6QrstTb8Tc90kTXqdhSahiEm+fwim+1UQOIbW2LfGSAOY5usvcrDRV9vIG+FfunyOI3JbefWQ40fy9JpBT8y29GDjaoH0AH03MlbLcDVcUuE1/aLHm7rG0NVvCDXDtxxO5rkJqKONmgpr9OyxRXeDjEnHG2xo5DuZAgs5R8FXrxp1iQ= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Aurelien Jarno , Laurent Vivier , Jiaxun Yang , Paolo Bonzini , Peter Maydell , Huacai Chen , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 01/11] target/mips: Remove helpers accessing SAAR registers Date: Fri, 9 Feb 2024 10:05:02 +0100 Message-ID: <20240209090513.9401-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240209090513.9401-1-philmd@linaro.org> References: <20240209090513.9401-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469615097100007 DisasContext::saar boolean is never set, so this code is not reachable. Remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/sysemu_helper.h.inc | 5 --- target/mips/tcg/sysemu/cp0_helper.c | 55 ----------------------------- target/mips/tcg/translate.c | 42 ---------------------- 3 files changed, 102 deletions(-) diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index f163af1eac..78f7272208 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -31,8 +31,6 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) DEF_HELPER_1(mfc0_tcschefback, tl, env) DEF_HELPER_1(mftc0_tcschefback, tl, env) DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) DEF_HELPER_1(mftc0_entryhi, tl, env) DEF_HELPER_1(mftc0_status, tl, env) DEF_HELPER_1(mftc0_cause, tl, env) @@ -57,7 +55,6 @@ DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ =20 DEF_HELPER_2(mtc0_index, void, env, tl) @@ -104,8 +101,6 @@ DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/c= p0_helper.c index 62f6fb4bf6..f8883a3515 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -371,22 +371,6 @@ target_ulong helper_mfc0_count(CPUMIPSState *env) return (int32_t)cpu_mips_get_count(env); } =20 -target_ulong helper_mfc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; - } - return 0; -} - -target_ulong helper_mfhc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; - } - return 0; -} - target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); @@ -514,13 +498,6 @@ target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, u= int32_t sel) return env->CP0_WatchHi[sel]; } =20 -target_ulong helper_dmfc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; - } - return 0; -} #endif /* TARGET_MIPS64 */ =20 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1108,38 +1085,6 @@ void helper_mtc0_saari(CPUMIPSState *env, target_ulo= ng arg1) } } =20 -void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target =3D env->CP0_SAARI & 0x3f; - if (target < 2) { - env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; - switch (target) { - case 0: - if (env->itu) { - itc_reconfigure(env->itu); - } - break; - } - } -} - -void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target =3D env->CP0_SAARI & 0x3f; - if (target < 2) { - env->CP0_SAAR[target] =3D - (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | - (env->CP0_SAAR[target] & 0x00000000ffffffffULL); - switch (target) { - case 0: - if (env->itu) { - itc_reconfigure(env->itu); - } - break; - } - } -} - void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 12094cc1e7..173b19a090 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -5151,17 +5151,6 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; - case CP0_REGISTER_09: - switch (sel) { - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mfhc0_saar(arg, tcg_env); - register_name =3D "SAAR"; - break; - default: - goto cp0_unimplemented; - } - break; case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: @@ -5252,17 +5241,6 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; - case CP0_REGISTER_09: - switch (sel) { - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mthc0_saar(tcg_env, arg); - register_name =3D "SAAR"; - break; - default: - goto cp0_unimplemented; - } - break; case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: @@ -5680,11 +5658,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); register_name =3D "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mfc0_saar(arg, tcg_env); - register_name =3D "SAAR"; - break; default: goto cp0_unimplemented; } @@ -6406,11 +6379,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_saari(tcg_env, arg); register_name =3D "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saar(tcg_env, arg); - register_name =3D "SAAR"; - break; default: goto cp0_unimplemented; } @@ -7180,11 +7148,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); register_name =3D "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_dmfc0_saar(arg, tcg_env); - register_name =3D "SAAR"; - break; default: goto cp0_unimplemented; } @@ -7892,11 +7855,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_saari(tcg_env, arg); register_name =3D "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saar(tcg_env, arg); - register_name =3D "SAAR"; - break; default: goto cp0_unimplemented; } --=20 2.41.0 From nobody Tue Oct 15 16:37:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469577538100001 Previous commit removed the MT*C0(SAAR) helpers which were the only calls to itc_reconfigure() out of hw/, we can reduce its scope and declare it statically. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/misc/mips_itu.h | 2 -- hw/misc/mips_itu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 5caed6cc36..3a7330ac07 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -79,6 +79,4 @@ struct MIPSITUState { /* Get ITC Configuration Tag memory region. */ MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu); =20 -void itc_reconfigure(struct MIPSITUState *tag); - #endif /* MIPS_ITU_H */ diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 37aea0e737..db1220f8e0 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -86,7 +86,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, u= nsigned size) return tag->ITCAddressMap[index]; } =20 -void itc_reconfigure(MIPSITUState *tag) +static void itc_reconfigure(MIPSITUState *tag) { uint64_t *am =3D &tag->ITCAddressMap[0]; MemoryRegion *mr =3D &tag->storage_io; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=philmd@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469613287100001 Previous commits removed the MT*C0(SAAR) helpers which were using CPUMIPSState::itu, we can now remove it too. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.h | 1 - hw/mips/cps.c | 1 - 2 files changed, 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index ef26fe03c7..6ec2ff4b97 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1184,7 +1184,6 @@ typedef struct CPUArchState { #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; void *irq[8]; - struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ =20 /* Loongson IOCSR memory */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4f12e23ab5..988ceaa0b9 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -96,7 +96,6 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) itu_present =3D true; /* Attach ITC Tag to the VP */ env->itc_tag =3D mips_itu_get_tag_region(&s->itu); - env->itu =3D &s->itu; } qemu_register_reset(main_cpu_reset, cpu); } --=20 2.41.0 From nobody Tue Oct 15 16:37:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469615105100008 This field is never set, so remove the unreachable code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.h | 1 - hw/misc/mips_itu.c | 6 ------ 2 files changed, 7 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 6ec2ff4b97..3b93591f7e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1174,7 +1174,6 @@ typedef struct CPUArchState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ - int saarp; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index db1220f8e0..d259a88d22 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -516,7 +516,6 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s =3D MIPS_ITU(dev); - CPUMIPSState *env; =20 if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -533,11 +532,6 @@ static void mips_itu_realize(DeviceState *dev, Error *= *errp) return; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469651617100003 Since previous commit the MIPSITUState::cpu0 field is not used anymore. Remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/misc/mips_itu.h | 1 - hw/mips/cps.c | 2 -- hw/misc/mips_itu.c | 5 ----- 3 files changed, 8 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 3a7330ac07..de7400c1fe 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -73,7 +73,6 @@ struct MIPSITUState { =20 /* SAAR */ uint64_t *saar; - ArchCPU *cpu0; }; =20 /* Get ITC Configuration Tag memory region. */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 988ceaa0b9..07b73b0a1f 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -103,8 +103,6 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU= ); - object_property_set_link(OBJECT(&s->itu), "cpu[0]", - OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index d259a88d22..9705efeafe 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -527,10 +527,6 @@ static void mips_itu_realize(DeviceState *dev, Error *= *errp) s->num_semaphores); return; } - if (!s->cpu0) { - error_setg(errp, "Missing 'cpu[0]' property"); - return; - } =20 s->cell =3D g_new(ITCStorageCell, get_num_cells(s)); } @@ -558,7 +554,6 @@ static Property mips_itu_properties[] =3D { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU = *), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.41.0 From nobody Tue Oct 15 16:37:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1707469623; cv=none; d=zohomail.com; s=zohoarc; b=cL/IJe4oYf8zaKn/thnX9E8UQQbvrRlxhrMJL4Lq8bFfKlpkZ9gblnVgLc0pIL5hl7XikBNagPRJl/7FCRqNQmGmAHtsfOxSlzJkWNjK42QFSYYIjQ40Yv12uqLsOQdLmhP25FuafCUwl2ZmJ5RIUBekyXqkOpc+p2huYu/EuOw= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469625148100003 This field is not set. Remove it along with the dead code it was guarding. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/misc/mips_itu.h | 3 --- hw/misc/mips_itu.c | 22 +++------------------- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index de7400c1fe..27c9a1090d 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -70,9 +70,6 @@ struct MIPSITUState { =20 /* ITU Control Register */ uint64_t icr0; - - /* SAAR */ - uint64_t *saar; }; =20 /* Get ITC Configuration Tag memory region. */ diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 9705efeafe..f8acfb3ee2 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -94,12 +94,6 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 - if (tag->saar) { - address =3D (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; - size =3D 1ULL << ((tag->saar[0] >> 1) & 0x1f); - is_enabled =3D tag->saar[0] & 1; - } - memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); @@ -158,12 +152,7 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain =3D 0) is 128 B */ - if (s->saar) { - return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & - ITC_ICR0_BLK_GRAIN_MASK); - } else { - return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); - } + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); } =20 static inline ITCStorageCell *get_cell(MIPSITUState *s, @@ -535,15 +524,10 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s =3D MIPS_ITU(dev); =20 - if (s->saar) { - s->saar[0] =3D 0x11 << 1; - s->icr0 =3D get_num_cells(s) << ITC_ICR0_CELL_NUM; - } else { - s->ITCAddressMap[0] =3D 0; - s->ITCAddressMap[1] =3D + s->ITCAddressMap[0] =3D 0; + s->ITCAddressMap[1] =3D ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.h | 1 - target/mips/sysemu/machine.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3b93591f7e..e621196ae1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -749,7 +749,6 @@ typedef struct CPUArchState { int32_t CP0_Count; uint32_t CP0_SAARI; #define CP0SAARI_TARGET 0 /* 5..0 */ - uint64_t CP0_SAAR[2]; #define CP0SAAR_BASE 12 /* 43..12 */ #define CP0SAAR_SIZE 1 /* 5..1 */ #define CP0SAAR_EN 0 diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c index 218f4c3a67..6d1299a89e 100644 --- a/target/mips/sysemu/machine.c +++ b/target/mips/sysemu/machine.c @@ -282,7 +282,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), - VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), + VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */ VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Status, MIPSCPU), --=20 2.41.0 From nobody Tue Oct 15 16:37:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=philmd@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469627144100005 DisasContext::saar boolean is never set, so this code is not reachable. Remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/sysemu_helper.h.inc | 1 - target/mips/tcg/sysemu/cp0_helper.c | 8 -------- target/mips/tcg/translate.c | 20 -------------------- 3 files changed, 29 deletions(-) diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 78f7272208..1861d538de 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -100,7 +100,6 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/c= p0_helper.c index f8883a3515..ded6c78e9a 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -1077,14 +1077,6 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulo= ng arg1) cpu_mips_store_count(env, arg1); } =20 -void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target =3D arg1 & 0x3f; - if (target <=3D 1) { - env->CP0_SAARI =3D target; - } -} - void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 173b19a090..3ba2101647 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -5653,11 +5653,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); - register_name =3D "SAARI"; - break; default: goto cp0_unimplemented; } @@ -6374,11 +6369,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_count(tcg_env, arg); register_name =3D "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saari(tcg_env, arg); - register_name =3D "SAARI"; - break; default: goto cp0_unimplemented; } @@ -7143,11 +7133,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); - register_name =3D "SAARI"; - break; default: goto cp0_unimplemented; } @@ -7850,11 +7835,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_count(tcg_env, arg); register_name =3D "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saari(tcg_env, arg); - register_name =3D "SAARI"; - break; default: goto cp0_unimplemented; } --=20 2.41.0 From nobody Tue Oct 15 16:37:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.h | 1 - target/mips/sysemu/machine.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e621196ae1..c65e5fa162 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -747,7 +747,6 @@ typedef struct CPUArchState { * CP0 Register 9 */ int32_t CP0_Count; - uint32_t CP0_SAARI; #define CP0SAARI_TARGET 0 /* 5..0 */ #define CP0SAAR_BASE 12 /* 43..12 */ #define CP0SAAR_SIZE 1 /* 5..1 */ diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c index 6d1299a89e..213fd637fc 100644 --- a/target/mips/sysemu/machine.c +++ b/target/mips/sysemu/machine.c @@ -281,7 +281,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), - VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), + VMSTATE_UNUSED(sizeof(uint32_t)), /* was CP0_SAARI */ VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */ VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), --=20 2.41.0 From nobody Tue Oct 15 16:37:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reported-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 93a78b8121..2b6646b339 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -49,7 +49,6 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; - bool saar; bool mi; int gi; } DisasContext; --=20 2.41.0 From nobody Tue Oct 15 16:37:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1707469643; cv=none; d=zohomail.com; s=zohoarc; b=ZnT0g8rX6MDeeFHhd9UdSeuyJv3nMNe5KSqW40ajXskcqmUntMVhKBEMYR2rlAFBG6PNyvJ+FtZeQXLjiEPr/eZ86cP1OkA35QxlB0LyDjW0Tqyb5VTj1tqhAzH8b7VBUU76p9SO/DQiSgfUyGHMcnmeqEElVdTLo/+JsSlveCk= ARC-Message-Signature: i=1; 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Fri, 09 Feb 2024 01:06:19 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXba0bkHEBVCjQNvRx1q2Nyy1RCIXN2+qbY3wMawd5vW8KefPyxQZtoRKCwm2YTNMjWaL6UQGqa60SkXsCL1UI7lKrpUt6B5I/bPdKjHoEAKz07aIOK+SQ7NlXVRj1kJaPVgDjnmyFmkJmjkPXYtzolEM14QXS5SCl+pMQRdUIw+3gr8G8k2nRRaqb4AseREJ1qrDc7JF+11uUm0YuetxxQQ4MujXLJeaLYhBqD27SBz+V+iHGMNXdrDt+H0kLdQdesGAeJzb4PfsRNLf9H1jK6Q1MIF6o7z9s3zacfNEw8sB9egUiGmiru6EbMKqI3vJWTCdQQaj/S7/Nk9HEQDvmqbWLnq1I= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Aurelien Jarno , Laurent Vivier , Jiaxun Yang , Paolo Bonzini , Peter Maydell , Huacai Chen , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 11/11] target/mips: Remove I6500 CPU definition Date: Fri, 9 Feb 2024 10:05:12 +0100 Message-ID: <20240209090513.9401-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240209090513.9401-1-philmd@linaro.org> References: <20240209090513.9401-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707469645270100003 I6500 support is incomplete as it lacks SAAR (Special Address Access Register) and DSPRAM (Data Scratch Pad RAM) features. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- docs/about/removed-features.rst | 5 +++++ tests/qtest/machine-none-test.c | 2 +- target/mips/cpu-defs.c.inc | 40 --------------------------------- 3 files changed, 6 insertions(+), 41 deletions(-) diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index 54081a6c19..d61b4c92dd 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -727,6 +727,11 @@ x86 ``Icelake-Client`` CPU (removed in 7.1) There isn't ever Icelake Client CPU, it is some wrong and imaginary one. Use ``Icelake-Server`` instead. =20 +MIPS I6500 CPU (removed in 9.0) +''''''''''''''''''''''''''''''' + +The I6500 support was never fully contributed. + System accelerators ------------------- =20 diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-tes= t.c index 31cc0bfb01..b653a0dd5c 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -37,7 +37,7 @@ static struct arch2cpu cpus_map[] =3D { { "mips", "4Kc" }, { "mipsel", "I7200" }, { "mips64", "20Kc" }, - { "mips64el", "I6500" }, + { "mips64el", "I6400" }, { "nios2", "FIXME" }, { "or1k", "or1200" }, { "ppc", "604" }, diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fbf787d8ce..ce2c01cbfa 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -778,46 +778,6 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS64R6, .mmu_type =3D MMU_TYPE_R4000, }, - { - .name =3D "I6500", - .CP0_PRid =3D 0x1B000, - .CP0_Config0 =3D MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_= AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU= ) | - (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA)= | - (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA)= | - (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 =3D MIPS_CONFIG2, - .CP0_Config3 =3D MIPS_CONFIG3 | (1U << CP0C3_M) | - (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | - (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULR= I) | - (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_V= Int), - .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | - (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), - .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP)= | - (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_G= I), - .CP0_Config5_rw_bitmask =3D (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI)= | - (1 << CP0C5_FRE) | (1 << CP0C5_UFE), - .CP0_LLAddr_rw_bitmask =3D 0, - .CP0_LLAddr_shift =3D 0, - .SYNCI_Step =3D 64, - .CCRes =3D 2, - .CP0_Status_rw_bitmask =3D 0x30D8FFFF, - .CP0_PageGrain =3D (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | - (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask =3D (1 << CP0PG_ELPA), - .CP0_EBaseWG_rw_bitmask =3D (1 << CP0EBase_WG), - .CP1_fcr0 =3D (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_= F64) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV= ), - .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .CP1_fcr31_rw_bitmask =3D 0x0103FFFF, - .MSAIR =3D 0x03 << MSAIR_ProcID, - .SEGBITS =3D 48, - .PABITS =3D 48, - .insn_flags =3D CPU_MIPS64R6, - .mmu_type =3D MMU_TYPE_R4000, - }, { .name =3D "Loongson-2E", .CP0_PRid =3D 0x6302, --=20 2.41.0