From nobody Tue Nov 26 14:32:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1707322241; cv=none; d=zohomail.com; s=zohoarc; b=W5eytHhujZcLqyvSFFUQEAanp+0fMh6tvRc8QrsfyOKQ+m5cSKHxXZpwUxOJxmDeWJxAuvh9osFUeGhyL8w2bJQxtl3YJVUirU38yMujCcfiyi68pgWbT8IEIKmUw2QI0CigKsczMIFrY7c2rHEI/kFl6Z8HlhbVrOPn6LzZLmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1707322241; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L9H45JJXTVFAmT2qZmG7Zk0B9tMbrlBmjncPqLX84rE=; b=WB1yaBoNRDMB/NiaA43nfPshmq3oO2z1aROSJ5H4Vr8Qh6gtFbZxoU/7yemw8aYCEnAnHGXPBNfmjQ+8VVQtLzUcMB/O6hMAHMqVTnTLG82EfMRo8iUzDMoR4xyGhrGqCJOtUvqTcQJHoGgMzCarmkexfUM9gDX14nYBtzc55r4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1707322241228843.4263622317031; Wed, 7 Feb 2024 08:10:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rXkU1-0003dy-It; Wed, 07 Feb 2024 11:09:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rXkTy-0003cd-QR; Wed, 07 Feb 2024 11:09:06 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rXkTw-0000gi-Da; Wed, 07 Feb 2024 11:09:06 -0500 Received: from pps.filterd (m0353728.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 417G2LC1030732; Wed, 7 Feb 2024 16:08:54 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3w4d1dr8ey-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Feb 2024 16:08:53 +0000 Received: from m0353728.ppops.net (m0353728.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 417G2ZjF031717; Wed, 7 Feb 2024 16:08:53 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3w4d1dr8dq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Feb 2024 16:08:53 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 417EbkYS005421; Wed, 7 Feb 2024 16:08:51 GMT Received: from smtprelay03.fra02v.mail.ibm.com ([9.218.2.224]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3w21akpj31-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Feb 2024 16:08:51 +0000 Received: from smtpav01.fra02v.mail.ibm.com (smtpav01.fra02v.mail.ibm.com [10.20.54.100]) by smtprelay03.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 417G8mD432506248 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 Feb 2024 16:08:48 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 82C0F20043; Wed, 7 Feb 2024 16:08:48 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D5D8420040; Wed, 7 Feb 2024 16:08:46 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 7 Feb 2024 16:08:46 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=L9H45JJXTVFAmT2qZmG7Zk0B9tMbrlBmjncPqLX84rE=; b=nhTRRVUwdZUeeJiVGGYlZf4uurOkLQk6/CIQXxeh2C1m1SaiQIjO3gaEWsKabX2+8Ow/ rslLy43bdNU5MvoS/RFDsfMAknoPWb7Of6D/m+gf1Rb48aIreK1gfeRI1CuBPz21zxuX zfeIzsST1pJzwCKSbNiz/rlkQEB5CyC20v4lPwhZGQlTpeo/R+g74epXvSWJ5GiJ8yGl AL1e1ReCGDn/T3gZ5aHTDVcvRxG/m1W/iFpXHLWBNzIBbRYTpz0SRCAFDTS49kyz11xE bIaFABmoUf3xubc8wZUcYF5SpkLdqA1wVfCzGXHurEE/siM7aOG3bBAzd5ehgSWjD8GS aw== From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, chalapathi.v@linux.ibm.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v1 1/5] hw/ppc: SPI responder model Date: Wed, 7 Feb 2024 10:08:29 -0600 Message-Id: <20240207160833.3437779-2-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240207160833.3437779-1-chalapathi.v@linux.ibm.com> References: <20240207160833.3437779-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 1vGlNCqTJnPynaPeb7XnL8aqSzeYbovC X-Proofpoint-ORIG-GUID: JE7MZJG9yvhmoALRCvYKr1QivTnB8ISC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-07_06,2024-02-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 impostorscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402070119 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1707322242244100001 Content-Type: text/plain; charset="utf-8" Serial pheripheral interface provides full-duplex synchronous serial communication between single controller and multiple responder devices. One SPI Controller is implemented and supported on a SPI Bus, there is no support for multiple controllers on the SPI bus. The current implemetation assumes that single responder is connected to bus, hence chip_select is not modelled. Signed-off-by: Chalapathi V --- include/hw/ppc/pnv_spi_responder.h | 109 +++++++++++++++++++ hw/ppc/pnv_spi_responder.c | 166 +++++++++++++++++++++++++++++ hw/ppc/meson.build | 1 + 3 files changed, 276 insertions(+) create mode 100644 include/hw/ppc/pnv_spi_responder.h create mode 100644 hw/ppc/pnv_spi_responder.c diff --git a/include/hw/ppc/pnv_spi_responder.h b/include/hw/ppc/pnv_spi_re= sponder.h new file mode 100644 index 0000000000..1cf7279aad --- /dev/null +++ b/include/hw/ppc/pnv_spi_responder.h @@ -0,0 +1,109 @@ +/* + * QEMU SPI Responder. + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * SPI provides full-duplex synchronous serial communication between single + * controller and multiple responder devices. One SPI Controller is + * implemented and supported on a SPI Bus, there is no support for multiple + * controllers on the SPI bus. + * + * The current implementation assumes that single responder is connected to + * bus, hence chip_select is not modelled. + */ + +#ifndef PPC_PNV_SPI_RESPONDER_H +#define PPC_PNV_SPI_RESPONDER_H + +#include "hw/qdev-core.h" +#include "qom/object.h" +#include "qemu/log.h" + +#define TYPE_PNV_SPI_RESPONDER "spi-responder" +OBJECT_DECLARE_TYPE(PnvSpiResponder, PnvSpiResponderClass, + PNV_SPI_RESPONDER) + +typedef struct xfer_buffer xfer_buffer; + +struct PnvSpiResponderClass { + DeviceClass parent_class; + + /* + * These methods are from controller to responder and implemented + * by all responders. + * Connect_controller/disconnect_controller methods are called by + * controller to initiate/stop the SPI transfer. + */ + void (*connect_controller)(PnvSpiResponder *responder, const char *por= t); + void (*disconnect_controller)(PnvSpiResponder *responder); + /* + * SPI transfer consists of a number of consecutive calls to the reque= st + * method. + * The parameter first is true on first call of the transfer and last = is on + * the final call of the transfer. Parameter bits and payload defines = the + * number of bits and data payload sent by controller. + * Responder returns the response payload. + */ + xfer_buffer *(*request)(PnvSpiResponder *responder, int first, int las= t, + int bits, xfer_buffer *payload); +}; + +struct PnvSpiResponder { + DeviceState parent_obj; +}; + +#define TYPE_SPI_BUS "spi-bus" +OBJECT_DECLARE_SIMPLE_TYPE(SpiBus, SPI_BUS) + +struct SpiBus { + BusState parent_obj; +}; + +/* + * spi_realize_and_unref: realize and unref an SPI responder + * @dev: SPI responder to realize + * @bus: SPI bus to put it on + * @errp: error pointer + */ +bool spi_realize_and_unref(DeviceState *dev, SpiBus *bus, Error **errp); + +/* + * spi_create_responder: create a SPI responder. + * @bus: SPI bus to put it on + * @name: name of the responder object. + * call spi_realize_and_unref() after creating the responder. + */ + +PnvSpiResponder *spi_create_responder(SpiBus *bus, const char *name); + +/* xfer_buffer */ +typedef struct xfer_buffer { + + uint32_t len; + uint8_t *data; + +} xfer_buffer; + +/* + * xfer_buffer_read_ptr: Increment the payload length and return the point= er + * to the data at offset + */ +uint8_t *xfer_buffer_write_ptr(xfer_buffer *payload, uint32_t offset, + uint32_t length); +/* xfer_buffer_read_ptr: Return the pointer to the data at offset */ +void xfer_buffer_read_ptr(xfer_buffer *payload, uint8_t **read_buf, + uint32_t offset, uint32_t length); +/* xfer_buffer_new: Allocate memory and return the pointer */ +xfer_buffer *xfer_buffer_new(void); +/* xfer_buffer_free: free the payload */ +void xfer_buffer_free(xfer_buffer *payload); + +/* Controller interface */ +SpiBus *spi_create_bus(DeviceState *parent, const char *name); +xfer_buffer *spi_request(SpiBus *bus, int first, int last, int bits, + xfer_buffer *payload); +bool spi_connect_controller(SpiBus *bus, const char *port); +bool spi_disconnect_controller(SpiBus *bus); +#endif /* PPC_PNV_SPI_SEEPROM_H */ diff --git a/hw/ppc/pnv_spi_responder.c b/hw/ppc/pnv_spi_responder.c new file mode 100644 index 0000000000..c3bc659b1b --- /dev/null +++ b/hw/ppc/pnv_spi_responder.c @@ -0,0 +1,166 @@ +/* + * QEMU PowerPC SPI Responder + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/ppc/pnv_spi_responder.h" +#include "qapi/error.h" + +static const TypeInfo spi_bus_info =3D { + .name =3D TYPE_SPI_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(SpiBus), +}; + +SpiBus *spi_create_bus(DeviceState *parent, const char *name) +{ + BusState *bus; + bus =3D qbus_new(TYPE_SPI_BUS, parent, name); + return SPI_BUS(bus); +} + +/* xfer_buffer_methods */ +xfer_buffer *xfer_buffer_new(void) +{ + xfer_buffer *payload =3D g_malloc0(sizeof(*payload)); + payload->data =3D g_malloc0(payload->len * sizeof(uint8_t)); + return payload; +} + +void xfer_buffer_free(xfer_buffer *payload) +{ + free(payload->data); + payload->data =3D NULL; + free(payload); +} + +uint8_t *xfer_buffer_write_ptr(xfer_buffer *payload, uint32_t offset, + uint32_t length) +{ + if (payload->len < (offset + length)) { + payload->len =3D offset + length; + payload->data =3D g_realloc(payload->data, + payload->len * sizeof(uint8_t)); + } + return &payload->data[offset]; +} + +void xfer_buffer_read_ptr(xfer_buffer *payload, uint8_t **read_buf, + uint32_t offset, uint32_t length) +{ + static uint32_t prev_len; + uint32_t offset_org =3D offset; + if (offset > payload->len) { + if (length < payload->len) { + offset =3D payload->len - length; + } else { + offset =3D 0; + length =3D payload->len; + } + qemu_log_mask(LOG_GUEST_ERROR, "Read offset(%d) exceeds buffer " + "length(%d), altered offset to %d and length to %d= to " + "read within buffer\n", offset_org, payload->len, + offset, length); + } else if ((offset + length) > payload->len) { + qemu_log_mask(LOG_GUEST_ERROR, "Read length(%d) bytes from offset = (%d)" + ", exceeds buffer length(%d)\n", length, offset, + payload->len); + length =3D payload->len - offset; + } + + if ((prev_len !=3D length) || (*read_buf =3D=3D NULL)) { + *read_buf =3D g_realloc(*read_buf, length * sizeof(uint8_t)); + prev_len =3D length; + } + *read_buf =3D &payload->data[offset]; +} + +/* Controller interface methods */ +bool spi_connect_controller(SpiBus *bus, const char *port) +{ + BusState *b =3D BUS(bus); + BusChild *kid; + QTAILQ_FOREACH(kid, &b->children, sibling) { + PnvSpiResponder *r =3D PNV_SPI_RESPONDER(kid->child); + PnvSpiResponderClass *rc =3D PNV_SPI_RESPONDER_GET_CLASS(r); + rc->connect_controller(r, port); + return true; + } + return false; +} +bool spi_disconnect_controller(SpiBus *bus) +{ + BusState *b =3D BUS(bus); + BusChild *kid; + QTAILQ_FOREACH(kid, &b->children, sibling) { + PnvSpiResponder *r =3D PNV_SPI_RESPONDER(kid->child); + PnvSpiResponderClass *rc =3D PNV_SPI_RESPONDER_GET_CLASS(r); + rc->disconnect_controller(r); + return true; + } + return false; +} + +xfer_buffer *spi_request(SpiBus *bus, + int first, int last, int bits, xfer_buffer *payload) +{ + BusState *b =3D BUS(bus); + BusChild *kid; + xfer_buffer *rsp_payload =3D NULL; + uint8_t *buf =3D NULL; + + QTAILQ_FOREACH(kid, &b->children, sibling) { + PnvSpiResponder *r =3D PNV_SPI_RESPONDER(kid->child); + PnvSpiResponderClass *rc =3D PNV_SPI_RESPONDER_GET_CLASS(r); + rsp_payload =3D rc->request(r, first, last, bits, payload); + return rsp_payload; + } + if (rsp_payload =3D=3D NULL) { + rsp_payload =3D xfer_buffer_new(); + } + buf =3D xfer_buffer_write_ptr(rsp_payload, 0, payload->len); + memset(buf, 0, payload->len); + return rsp_payload; +} + +/* create and realise spi responder device */ +bool spi_realize_and_unref(DeviceState *dev, SpiBus *bus, Error **errp) +{ + return qdev_realize_and_unref(dev, &bus->parent_obj, errp); +} + +PnvSpiResponder *spi_create_responder(SpiBus *bus, const char *name) +{ + DeviceState *dev =3D qdev_new(name); + + spi_realize_and_unref(dev, bus, &error_fatal); + return PNV_SPI_RESPONDER(dev); +} + +static void pnv_spi_responder_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "PowerNV SPI RESPONDER"; +} + +static const TypeInfo pnv_spi_responder_info =3D { + .name =3D TYPE_PNV_SPI_RESPONDER, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(PnvSpiResponder), + .class_init =3D pnv_spi_responder_class_init, + .abstract =3D true, + .class_size =3D sizeof(PnvSpiResponderClass), +}; + +static void pnv_spi_responder_register_types(void) +{ + type_register_static(&pnv_spi_responder_info); + type_register_static(&spi_bus_info); +} + +type_init(pnv_spi_responder_register_types); diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index eba3406e7f..9bfd5a5613 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -53,6 +53,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_bmc.c', 'pnv_homer.c', 'pnv_pnor.c', + 'pnv_spi_responder.c', )) # PowerPC 4xx boards ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( --=20 2.31.1