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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v8-20020a1709063bc800b00a3515b35be4sm702284ejf.104.2024.02.07.04.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 04:23:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1707308581; x=1707913381; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yqXN7kP1hctkf0dzKT9GxG/h8OL9Zq0Ugm+1HgJ+nt4=; b=iCBfTRMSqYLuk3KBgu05pjo21HhQmAHgKCpZ/Ox6OgRoLou2BXbDy2Am9EZJ/eR1Q9 4s3i2pLqoepkRjJDNEPbBB7jM+IA8hq8WV1YvQVVeJfqXkr7GAqFHPtac9vnJGl9iVAe dP7Z5B5I8KOPDCERYDfhiWt8DE2lDeX+uNWdPj8yMlOq7cUsXmXRnxY8bIjHqu5KjdAn rTGmDvnU1OrskEZdIYMvqLhLNWWfP+p85FUfcqU4tARytFXhL3UG1w/grHWxNIq+Wvpj B4kb2cCrTskT0FhKHbOLwctMRmhZc2I5gUDHPy5c223aTD344nSItHaW9Y8vkOBbvzwk DmYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707308581; x=1707913381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yqXN7kP1hctkf0dzKT9GxG/h8OL9Zq0Ugm+1HgJ+nt4=; b=ok6Gl0unbVNClQXb0XJsLNx5eAhDFYrKOXUbzUmDgmHgwG25oyXHN/sJlarpkH2uXx mxDaUsjCcocd5tQrqnDlA9Z+mvD0oeU1HZ9S63tGomvLAUEgaqDzBsIWH/kyRJcQbO44 gt+2deLL13EZV5gsa70VDCebvFW4tJlvpAw8bgWASGKWCHhr567vjSpaBGQxjJn5W2b/ fxqDWEtlDOEyoroN2PTqpuormFGIk87W3Ju9HG5lLlhRPfba1L/PJFkhZhcPRADNTA+k mM9z8Zp0KjZ3E6Nga1XTyJQUEHCsLRLYA4G2qI1GT41PjZRde5thV+fFZ5ihe7j4gXXk TfNA== X-Gm-Message-State: AOJu0YzqO3rP83IWMXacavDHbtRO93s2ZcQUq8swqDkNHmedWSnB062I oHBOMU8dYHVUlJe37iW79och6YC1NxDP13QEDzCBw3baKPOk0UDlJ1NQLk6spJ0= X-Google-Smtp-Source: AGHT+IFFBB0SRgcniQOnugEhExpT2pSJTnPazCTWJ5zZSz6Am93L+piFzh2Z4SvrCpsEm2K+T6lCHg== X-Received: by 2002:a05:6512:3e01:b0:511:577d:10de with SMTP id i1-20020a0565123e0100b00511577d10demr5031414lfv.37.1707308581096; Wed, 07 Feb 2024 04:23:01 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXOdJc7rgpLQkz92BuDWuM+J+PVREOGSDid42I63YE6Py5MtQF5JDzOGw++eB8OVXEBMFsXfD3rtDBz269RhX1qGMzKVZ4vytN4eeCbFpSNzaal8/p/yRfaKJsSI74AMVS6hculrU7T95FNmUMV2wZvu7b4MYEad2pxjSQEN9ZAlI2oczhg45TO+t9y3W1Nb/Ab9IWS8MUI7F7WLL/Sw8tFZLLo5Z4pccqwLukrHanuL/1LdSwdaGIi82HUblYVFRqmjgadFUv8+7Wea1C5CD4Ylg9+it6ZGtecWO08DwKOGeMiV6tSMMUemkLjGv6dIq4VXsq91rIE9UhGNpOnw26earFY869gsd2mhKMnWqoW/OZSXDd7juGRx3Age6qAhox+GFlJ58CyPsunyvBAoLbubZmlGZbAXDQvmGsS0VTIuF2m6ampNX4= From: =?UTF-8?q?Christoph=20M=C3=BCllner?= To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Daniel Henrique Barboza , Andrew Jones Cc: Palmer Dabbelt , =?UTF-8?q?Christoph=20M=C3=BCllner?= , Weiwei Li , Liu Zhiwei Subject: [PATCH 1/2] RISC-V: Add support for Ztso Date: Wed, 7 Feb 2024 13:22:54 +0100 Message-ID: <20240207122256.902627-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240207122256.902627-1-christoph.muellner@vrull.eu> References: <20240207122256.902627-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=christoph.muellner@vrull.eu; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1707308649277100001 From: Palmer Dabbelt The Ztso extension is already ratified, this adds it as a CPU property and adds various fences throughout the port in order to allow TSO targets to function on weaker hosts. We need no fences for AMOs as they're already SC, the places we need barriers are described. These fences are placed in the RISC-V backend rather than TCG as is planned for x86-on-arm64 because RISC-V allows heterogeneous (and likely soon dynamic) hart memory models. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Palmer Dabbelt Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++--- target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++-- target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++ target/riscv/translate.c | 3 +++ 6 files changed, 48 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1b8d001d23..b679ecd8c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -143,6 +143,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso), ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), @@ -1488,6 +1489,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false), MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false), MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false), + MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false), =20 MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false), MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 833bf58217..afba8ed0b2 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -71,6 +71,7 @@ struct RISCVCPUConfig { bool ext_zihintntl; bool ext_zihintpause; bool ext_zihpm; + bool ext_ztso; bool ext_smstateen; bool ext_sstc; bool ext_svadu; diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 267930e5bc..4a9e4591d1 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -40,7 +40,11 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, Mem= Op mop) tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); - if (a->aq) { + /* + * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC= as + * AMOs. Instead treat them like loads. + */ + if (a->aq || ctx->ztso) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } =20 @@ -76,9 +80,10 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, Mem= Op mop) gen_set_label(l1); /* * Address comparison failure. However, we still need to - * provide the memory barrier implied by AQ/RL. + * provide the memory barrier implied by AQ/RL/TSO. */ - tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL); + TCGBar bar_strl =3D (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0; + tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl); gen_set_gpr(ctx, a->rd, tcg_constant_tl(1)); =20 gen_set_label(l2); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index faf6d65064..ad40d3e87f 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -266,12 +266,20 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *= a, MemOp memop) =20 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { + bool out; + decode_save_opc(ctx); if (get_xl(ctx) =3D=3D MXL_RV128) { - return gen_load_i128(ctx, a, memop); + out =3D gen_load_i128(ctx, a, memop); } else { - return gen_load_tl(ctx, a, memop); + out =3D gen_load_tl(ctx, a, memop); + } + + if (ctx->ztso) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } + + return out; } =20 static bool trans_lb(DisasContext *ctx, arg_lb *a) @@ -328,6 +336,10 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a,= MemOp memop) TCGv addr =3D get_address(ctx, a->rs1, a->imm); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 + if (ctx->ztso) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; } diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 9e101ab434..742008f58b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -636,8 +636,28 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, u= int32_t data, tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 + /* + * According to the specification + * + * Additionally, if the Ztso extension is implemented, then vector m= emory + * instructions in the V extension and Zve family of extensions foll= ow + * RVTSO at the instruction level. The Ztso extension does not + * strengthen the ordering of intra-instruction element accesses. + * + * as a result neither ordered nor unordered accesses from the V + * instructions need ordering within the loop but we do still need bar= riers + * around the loop. + */ + if (is_store && s->ztso) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + fn(dest, mask, base, tcg_env, desc); =20 + if (!is_store && s->ztso) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + if (!is_store) { mark_vs_dirty(s); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 177418b2b9..ea5d52b2ef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -109,6 +109,8 @@ typedef struct DisasContext { /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; + /* Ztso */ + bool ztso; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1196,6 +1198,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); + ctx->ztso =3D cpu->cfg.ext_ztso; ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; --=20 2.43.0 From nobody Tue Nov 26 12:29:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=vrull.eu ARC-Seal: i=1; a=rsa-sha256; t=1707308670; cv=none; d=zohomail.com; s=zohoarc; b=mQl5qYGxjzcn6+VHTR6q1ZZcZKwoXt2NfKQTUwJotoMf67F7LV/SoAxAbFUb60ThoL4QgsqoJBECfKJEr2qbnn5EphToe1F6LZCGwh+FsRn6MjK2cxsmr/OdQZ1/lO5v6ZfHiEmTbIzZh0HnECKkuw5uvDMF/dnlwkrGY3mGicE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1707308670; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=M2mD/C0rP4kd3MQb0al+PrLOXSiBVfqFrpY8FsaZgMg=; b=SFa3eqIsQmWWIt6c4laa/zpr3Uc5l8FeyFcGpEm8mtbMD/bQd5BgejtsH68g2fE4LFfSmdeChaAhCb4kd1a2o3f0o344aTS2kaEK/gWxjBD/ByPtIEkqkfu6Pkr/D2BA2A7tVV7AG9+FZTdjGaeUMQGZnAB9/XDNNAnMQHeLgII= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170730867073531.64417622134897; Wed, 7 Feb 2024 04:24:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rXgxM-0006vS-DA; Wed, 07 Feb 2024 07:23:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rXgxF-0006tI-J9 for qemu-devel@nongnu.org; Wed, 07 Feb 2024 07:23:06 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rXgxE-0007D6-51 for qemu-devel@nongnu.org; Wed, 07 Feb 2024 07:23:05 -0500 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-a3884b1a441so48536766b.2 for ; Wed, 07 Feb 2024 04:23:03 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. 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Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- linux-user/syscall.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 3ba20f99ad..24fa11d946 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8826,6 +8826,7 @@ static int do_getdents64(abi_long dirfd, abi_long arg= 2, abi_long count) #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) +#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) =20 @@ -8940,6 +8941,8 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *en= v, RISCV_HWPROBE_EXT_ZVFHMIN : 0; value |=3D cfg->ext_zfa ? RISCV_HWPROBE_EXT_ZFA : 0; + value |=3D cfg->ext_ztso ? + RISCV_HWPROBE_EXT_ZTSO : 0; value |=3D cfg->ext_zacas ? RISCV_HWPROBE_EXT_ZACAS : 0; value |=3D cfg->ext_zicond ? --=20 2.43.0