From nobody Tue Nov 26 15:37:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1707226340; cv=none; d=zohomail.com; s=zohoarc; b=DTfUtsahNxmTFKM/1BI724wYg9ZYFwPl4MpX/WaVwJNnnhzkWWZiXUMqPdmr/T28q8UBt+Ms2jOiNT+kaTAxjaQdsULQo8KUGVoAniROUjXCo6JNmWynNEs0yKUb0wHfh17qYdHp0c9mCvNtkIMpGvIJ3f+K/+KosJ0Ve7gedV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1707226340; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ERolA0aC2wCykerxlApD+LMGSL7zywOWVrO1yRbs12k=; b=Hq1xt8EJOjDRToRVryc/6O0Dc10C75rSGyipUeX/N8rSlPKT4XeCAtUb2mw4Cz/9Bg3FnEuX9XYYyF2QBJ+b/n11n6nYzUX+UeDbUR+drDKkKEvm5t6Nn/60P3ChfyLLzc9BCuabyVgOZfj3sPYN0t4dau/09zNKjmLZBPN0eGU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1707226340228297.017465063126; Tue, 6 Feb 2024 05:32:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rXLWG-0000nz-Mx; Tue, 06 Feb 2024 08:29:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rXLWB-0000Xz-Cw for qemu-devel@nongnu.org; Tue, 06 Feb 2024 08:29:43 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rXLW5-0008Eh-VU for qemu-devel@nongnu.org; Tue, 06 Feb 2024 08:29:43 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-33b401fd72bso1391056f8f.3 for ; Tue, 06 Feb 2024 05:29:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a056000108700b0033b470a137esm1492932wrw.79.2024.02.06.05.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 05:29:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707226176; x=1707830976; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ERolA0aC2wCykerxlApD+LMGSL7zywOWVrO1yRbs12k=; b=eHwc1qqECwaZZJPPgP975nXyJdjC7cRyzHyy9ul/mmxN0KWFAkB9AtegOhxNFn2rM/ ZvPPBJDiKPEI9SiPKuwf77gQ9CD04VRDSyzreLfttM+gFjb+/p15AvIC0YxMouAiruOC QmPgHN1g12ye4+5SHeA6ppzRz1EhQTWv/aP52G3UFy3/wNzgNiyFN2Qxkpircf9apsQ5 Yu9adJGE1sEbqrzvM5bK2Hw0k5J4OebplQqdg/g4VcR2H895LBFfCeC6t41hUk9uygdb TpVU9wUaQwSHsNRHPuxAZH4vglqe5O6mNyQOyLEHu+QvQuXXMDcWSmVGdPCAYoRfhwKI HLGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707226176; x=1707830976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ERolA0aC2wCykerxlApD+LMGSL7zywOWVrO1yRbs12k=; b=pdTtGxcxUfwlE8gm8S/qxgKCk7xnqvTyl5csc5onuHobayUSkeVefGasC7JLuBplqg e9oGHNShtZvTP/xDq+Wob00miQPYZYr0cFXfThSSs+crU0ihOBOE2kMCzngaLVniveE8 fNjzgZrK9HWzQ6gl/SqVKSnBJmTsq6394DlkWJkp9jyOrhGsd8Qt4jWMFkR5k1c5k8Cr ByNxtlmvhm3Fz+5C9JDa56y+t96a+bBkFnD08BBDmQb/qYh2riqkv/dNQo/+WMhUUEVr iKtSbh+8NqrdBk4WLR9qyPkOk7LYAf4ybhD1EAAGP0yaRxcn1/xvXgOCqmPiZp3kTF2U 2Rmg== X-Gm-Message-State: AOJu0Ywul2sYPvSYhZDyeVOZJnCKd6GJsYnyx+bYOidn01nW+HAOyEr6 93bHlGyau0Rni2FH1/SgtvAL6qt89UPVYZEmYzZ0+8kti3r6f+Uk/0k9Pv3iVCeXxxEUexa0f4D W X-Google-Smtp-Source: AGHT+IGusJCX7b8/iZoagEKCYVoDy75CckieKXbkCvdxMEXJZ5NGHiV+etbG8PEgWhdEfKuMZM+IJQ== X-Received: by 2002:a5d:518b:0:b0:33b:d01:3e39 with SMTP id k11-20020a5d518b000000b0033b0d013e39mr1394926wrv.68.1707226176561; Tue, 06 Feb 2024 05:29:36 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCWQ7cUZwji/KkOiSduMjEyoc43UFh/phqduPO3TN6GPYYYL/RLxDwqJNZmYAp/CNSH2/SqfV1hZz6J0Sq2b01Exax5xEho= From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/13] hw/arm/mps3r: Initial skeleton for mps3-an536 board Date: Tue, 6 Feb 2024 13:29:26 +0000 Message-Id: <20240206132931.38376-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206132931.38376-1-peter.maydell@linaro.org> References: <20240206132931.38376-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707226341203100003 Content-Type: text/plain; charset="utf-8" The AN536 is another FPGA image for the MPS3 development board. Unlike the existing FPGA images we already model, this board uses a Cortex-R family CPU, and it does not use any equivalent to the M-profile "Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c. It's therefore more convenient for us to model it as a completely separate C file. This commit adds the basic skeleton of the board model, and the code to create all the RAM and ROM. We assume that we're probably going to want to add more images in future, so use the same base class/subclass setup that mps2-tz.c uses, even though at the moment there's only a single subclass. Following commits will add the CPUs and the peripherals. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 3 +- configs/devices/arm-softmmu/default.mak | 1 + hw/arm/mps3r.c | 239 ++++++++++++++++++++++++ hw/arm/Kconfig | 5 + hw/arm/meson.build | 1 + 5 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 hw/arm/mps3r.c diff --git a/MAINTAINERS b/MAINTAINERS index 2f9741b898e..8219ed9068c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -819,12 +819,13 @@ F: include/hw/misc/imx7_*.h F: hw/pci-host/designware.c F: include/hw/pci-host/designware.h =20 -MPS2 +MPS2 / MPS3 M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained F: hw/arm/mps2.c F: hw/arm/mps2-tz.c +F: hw/arm/mps3r.c F: hw/misc/mps2-*.c F: include/hw/misc/mps2-*.h F: hw/arm/armsse.c diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-= softmmu/default.mak index 023faa2f750..6ee31bc1ab9 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -13,6 +13,7 @@ CONFIG_ARM_VIRT=3Dy # CONFIG_INTEGRATOR=3Dn # CONFIG_FSL_IMX31=3Dn # CONFIG_MUSICPAL=3Dn +# CONFIG_MPS3R=3Dn # CONFIG_MUSCA=3Dn # CONFIG_CHEETAH=3Dn # CONFIG_SX1=3Dn diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c new file mode 100644 index 00000000000..888a846d23c --- /dev/null +++ b/hw/arm/mps3r.c @@ -0,0 +1,239 @@ +/* + * Arm MPS3 board emulation for Cortex-R-based FPGA images. + * (For M-profile images see mps2.c and mps2tz.c.) + * + * Copyright (c) 2017 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * The MPS3 is an FPGA based dev board. This file handles FPGA images + * which use the Cortex-R CPUs. We model these separately from the + * M-profile images, because on M-profile the FPGA image is based on + * a "Subsystem for Embedded" which is similar to an SoC, whereas + * the R-profile FPGA images don't have that abstraction layer. + * + * We model the following FPGA images here: + * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note = AN536 + * + * Application Note AN536: + * https://developer.arm.com/documentation/dai0536/latest/ + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "cpu.h" +#include "hw/boards.h" +#include "hw/arm/boot.h" + +/* Define the layout of RAM and ROM in a board */ +typedef struct RAMInfo { + const char *name; + hwaddr base; + hwaddr size; + int mrindex; /* index into rams[]; -1 for the system RAM block */ + int flags; +} RAMInfo; + +/* + * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit + * emulation of that much guest RAM, so artificially make it smaller. + */ +#if HOST_LONG_BITS =3D=3D 32 +#define MPS3_DDR_SIZE (1 * GiB) +#else +#define MPS3_DDR_SIZE (3 * GiB) +#endif + +/* + * Flag values: + * IS_MAIN: this is the main machine RAM + * IS_ROM: this area is read-only + */ +#define IS_MAIN 1 +#define IS_ROM 2 + +#define MPS3R_RAM_MAX 9 + +typedef enum MPS3RFPGAType { + FPGA_AN536, +} MPS3RFPGAType; + +struct MPS3RMachineClass { + MachineClass parent; + MPS3RFPGAType fpga_type; + const RAMInfo *raminfo; +}; + +struct MPS3RMachineState { + MachineState parent; + MemoryRegion ram[MPS3R_RAM_MAX]; +}; + +#define TYPE_MPS3R_MACHINE "mps3r" +#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536") + +OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE) + +static const RAMInfo an536_raminfo[] =3D { + { + .name =3D "ATCM", + .base =3D 0x00000000, + .size =3D 0x00008000, + .mrindex =3D 0, + }, { + /* We model the QSPI flash as simple ROM for now */ + .name =3D "QSPI", + .base =3D 0x08000000, + .size =3D 0x00800000, + .flags =3D IS_ROM, + .mrindex =3D 1, + }, { + .name =3D "BRAM", + .base =3D 0x10000000, + .size =3D 0x00080000, + .mrindex =3D 2, + }, { + .name =3D "DDR", + .base =3D 0x20000000, + .size =3D MPS3_DDR_SIZE, + .mrindex =3D -1, + }, { + .name =3D "ATCM0", + .base =3D 0xee000000, + .size =3D 0x00008000, + .mrindex =3D 3, + }, { + .name =3D "BTCM0", + .base =3D 0xee100000, + .size =3D 0x00008000, + .mrindex =3D 4, + }, { + .name =3D "CTCM0", + .base =3D 0xee200000, + .size =3D 0x00008000, + .mrindex =3D 5, + }, { + .name =3D "ATCM1", + .base =3D 0xee400000, + .size =3D 0x00008000, + .mrindex =3D 6, + }, { + .name =3D "BTCM1", + .base =3D 0xee500000, + .size =3D 0x00008000, + .mrindex =3D 7, + }, { + .name =3D "CTCM1", + .base =3D 0xee600000, + .size =3D 0x00008000, + .mrindex =3D 8, + }, { + .name =3D NULL, + } +}; + +static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, + const RAMInfo *raminfo) +{ + /* Return an initialized MemoryRegion for the RAMInfo. */ + MemoryRegion *ram; + + if (raminfo->mrindex < 0) { + /* Means this RAMInfo is for QEMU's "system memory" */ + MachineState *machine =3D MACHINE(mms); + assert(!(raminfo->flags & IS_ROM)); + return machine->ram; + } + + assert(raminfo->mrindex < MPS3R_RAM_MAX); + ram =3D &mms->ram[raminfo->mrindex]; + + memory_region_init_ram(ram, NULL, raminfo->name, + raminfo->size, &error_fatal); + if (raminfo->flags & IS_ROM) { + memory_region_set_readonly(ram, true); + } + return ram; +} + +static void mps3r_common_init(MachineState *machine) +{ + MPS3RMachineState *mms =3D MPS3R_MACHINE(machine); + MPS3RMachineClass *mmc =3D MPS3R_MACHINE_GET_CLASS(mms); + MemoryRegion *sysmem =3D get_system_memory(); + + for (const RAMInfo *ri =3D mmc->raminfo; ri->name; ri++) { + MemoryRegion *mr =3D mr_for_raminfo(mms, ri); + memory_region_add_subregion(sysmem, ri->base, mr); + } +} + +static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) +{ + /* + * Set mc->default_ram_size and default_ram_id from the + * information in mmc->raminfo. + */ + MachineClass *mc =3D MACHINE_CLASS(mmc); + const RAMInfo *p; + + for (p =3D mmc->raminfo; p->name; p++) { + if (p->mrindex < 0) { + /* Found the entry for "system memory" */ + mc->default_ram_size =3D p->size; + mc->default_ram_id =3D p->name; + return; + } + } + g_assert_not_reached(); +} + +static void mps3r_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->init =3D mps3r_common_init; +} + +static void mps3r_an536_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS3RMachineClass *mmc =3D MPS3R_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-r52"), + NULL + }; + + mc->desc =3D "ARM MPS3 with AN536 FPGA image for Cortex-R52"; + mc->default_cpus =3D 2; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-r52"); + mc->valid_cpu_types =3D valid_cpu_types; + mmc->raminfo =3D an536_raminfo; + mps3r_set_default_ram_info(mmc); +} + +static const TypeInfo mps3r_machine_types[] =3D { + { + .name =3D TYPE_MPS3R_MACHINE, + .parent =3D TYPE_MACHINE, + .abstract =3D true, + .instance_size =3D sizeof(MPS3RMachineState), + .class_size =3D sizeof(MPS3RMachineClass), + .class_init =3D mps3r_class_init, + }, { + .name =3D TYPE_MPS3R_AN536_MACHINE, + .parent =3D TYPE_MPS3R_MACHINE, + .class_init =3D mps3r_an536_class_init, + }, +}; + +DEFINE_TYPES(mps3r_machine_types); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index db08a00a45b..8b45dc116ae 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -106,6 +106,11 @@ config MAINSTONE select PFLASH_CFI01 select SMC91C111 =20 +config MPS3R + bool + default y + depends on TCG && ARM + config MUSCA bool default y diff --git a/hw/arm/meson.build b/hw/arm/meson.build index c4017790670..a16d3479055 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -8,6 +8,7 @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highban= k.c')) arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) +arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c')) arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-= h405.c')) --=20 2.34.1