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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a056000108700b0033b470a137esm1492932wrw.79.2024.02.06.05.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 05:29:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707226174; x=1707830974; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=h7YaNX76JwqZEJT0rHKxb3cowkocOAyFr6+DgbOiGaE=; b=VRAiac+QPyabZ6xxWZZoUs3NPPwiZkIzarYqWlx6s4yOMojHN+Eu29em/60mmub/DJ zn2j2SM4E9LbLy189ysGlihKb4afCpgV1tsx/lcuy09Bc9GnSKdwfrFikBE6vZjPAZPx +rTGs9mwFYzKjHQhVHicnbh3dWfNEwLETlfLW4/mxtDYFsuOpH1qu9KJMgESyMmglKuB otaYcUpSawbJq2180wHTgqJORsIol9rzUUUfM7uVT4pVhf2Sq5MdRtd7Oe4CpKG8PxEr C62nKQP0fv/9SUmMVQbDrPcEypQiTPGVaS1CxC7uX3ShBQwiqgP1RuqxauLyj7yqx3Vy or/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707226174; x=1707830974; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h7YaNX76JwqZEJT0rHKxb3cowkocOAyFr6+DgbOiGaE=; b=VgG7JCM0kUpU2409xOofzqDU8rCO2FnD8vA3WaQLios/h9Z/WoDh/Hiy4lp6VU/Xa1 rAmu8NeUg4b2Em46ECU5RwjNb9YE51c02lVmT7ocJxXAXfUr+qQ/hbykP+Xqr96jG2sC QylBopA/L0c6UuR+a2RD72B0FKRLaYERjMRzr5dw88iOdr++pnbAllDK09veZdVZpYwJ vuaRLRyToxAGQhvweNEITXGLDtem/e17ZBEGi3FRdxHUl/qRn7vnbAntfhYhEjxBWOEa HpZmjoyezkesIrjYsjMc9HS4/Z/4ne/Rr1K3ezmxjQz95CLGJC9ls7KButACPoUy6+px DvKw== X-Gm-Message-State: AOJu0YzeFXnqttssyirKxm6ZvP3hP7FvskeO4czzIRBeOVKAT60bHrcS TihghJJUdsS+yPftpulOA+j6VWfZgcdtCBxTyaqS1hwFNucycoSlEirgdWivbnU= X-Google-Smtp-Source: AGHT+IHobB3hvfz2GrLp2gza7bUNw8EVpcsVCuiE7ZdgxPwSjoBlnjPaA964QgtrhrKlH5HskbuLXw== X-Received: by 2002:a5d:6682:0:b0:33a:eec4:c0c6 with SMTP id l2-20020a5d6682000000b0033aeec4c0c6mr1251743wru.12.1707226173986; Tue, 06 Feb 2024 05:29:33 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCU1s9rGIXOur/AiDMftwLUWKqfXHFK+gVeCGoeqCaVAy60DXB5ga24x9kX2ATYiBBTeQQ1hZeEMH/J+dtY5P+cDS7KIdCU= From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/13] target/arm: Add Cortex-R52 IMPDEF sysregs Date: Tue, 6 Feb 2024 13:29:21 +0000 Message-Id: <20240206132931.38376-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206132931.38376-1-peter.maydell@linaro.org> References: <20240206132931.38376-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707226256867100003 Content-Type: text/plain; charset="utf-8" Add the Cortex-R52 IMPDEF sysregs, by defining them here and also by enabling the AUXCR feature which defines the ACTLR and HACTLR registers. As is our usual practice, we make these simple reads-as-zero stubs for now. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 311d654cdce..6eb08a41b01 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -800,6 +800,111 @@ static void cortex_r5_initfn(Object *obj) define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } =20 +static const ARMCPRegInfo cortex_r52_cp_reginfo[] =3D { + { .name =3D "CPUACTLR", .cp =3D 15, .opc1 =3D 0, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "IMP_ATCMREGIONR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_BTCMREGIONR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_CTCMREGIONR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_CSCTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_BPCTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_MEMPROTCLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_SLAVEPCTLR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 11, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_PERIPHREGIONR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_FLASHIFREGIONR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_BUILDOPTR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_PINOPTR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_QOSR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_BUSTIMEOUTR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_INTMONR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_ICERR0", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_ICERR1", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_DCERR0", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_DCERR1", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_TCMERR0", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_TCMERR1", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_TCMSYNDR0", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_TCMSYNDR1", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_FLASHERR0", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_FLASHERR1", + .cp =3D 15, .opc1 =3D 2, .crn =3D 15, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_CDBGDR0", + .cp =3D 15, .opc1 =3D 3, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_CBDGBR1", + .cp =3D 15, .opc1 =3D 3, .crn =3D 15, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_TESTR0", + .cp =3D 15, .opc1 =3D 4, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "IMP_TESTR1", + .cp =3D 15, .opc1 =3D 4, .crn =3D 15, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP, .resetvalue =3D 0 }, + { .name =3D "IMP_CDBGDCI", + .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm =3D 15, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP, .resetvalue =3D 0 }, + { .name =3D "IMP_CDBGDCT", + .cp =3D 15, .opc1 =3D 3, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP, .resetvalue =3D 0 }, + { .name =3D "IMP_CDBGICT", + .cp =3D 15, .opc1 =3D 3, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP, .resetvalue =3D 0 }, + { .name =3D "IMP_CDBGDCD", + .cp =3D 15, .opc1 =3D 3, .crn =3D 15, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP, .resetvalue =3D 0 }, + { .name =3D "IMP_CDBGICD", + .cp =3D 15, .opc1 =3D 3, .crn =3D 15, .crm =3D 4, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP, .resetvalue =3D 0 }, +}; + + static void cortex_r52_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -810,6 +915,7 @@ static void cortex_r52_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_AUXCR); cpu->midr =3D 0x411fd133; /* r1p3 */ cpu->revidr =3D 0x00000000; cpu->reset_fpsid =3D 0x41034023; @@ -840,6 +946,8 @@ static void cortex_r52_initfn(Object *obj) =20 cpu->pmsav7_dregion =3D 16; cpu->pmsav8r_hdregion =3D 16; + + define_arm_cp_regs(cpu, cortex_r52_cp_reginfo); } =20 static void cortex_r5f_initfn(Object *obj) --=20 2.34.1