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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a056000108700b0033b470a137esm1492932wrw.79.2024.02.06.05.29.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 05:29:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707226178; x=1707830978; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=J5yMl9ruByZ2cE+u8xokLZN5yHG5tcwG0U9htQdpN5s=; b=C4jwr3tIuzk9Hwwqph03lWD6AOZ2oaIWffPAJIgdU4w3QiokXpr78aDkunZpiYA7+l FMZQ6RspLhjjsJBUM2kRSKZ+NgvVaJAYqYmemYEC39MdvKY0mFNsKkMCalxaNHsdeR36 v8sSsBol54JRttECsE3yyFPV5/6Iwo13y7HrbGRhW1tMZYLiecS6V6XkaOZKEOX1FTnI pTWPm3lFukf4kvVmZqCWlu3dHomci5A1qWcn8UX0VkwzrYGLne4LjBXhkvhd/cB6h1s4 6LxDKIO1UXoIgO8Bwgs52FkZbVha0UESX5SjZlamLnXH6hOeXOzqw7f2bdZwBnFGNMQq 7tsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707226178; x=1707830978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J5yMl9ruByZ2cE+u8xokLZN5yHG5tcwG0U9htQdpN5s=; b=BjZHT7k9BWfYX/wjFnkrVMA9rYQnpyMoMwUiCTlNohAaA9w3fTCSJ5B750mCEl9+VI Lg5E6kRGkoeL0Bki9LoIQ1et5b/hz7vQp7JW8HSjgh4AOtsqF/Ugy3h7V71a342XXwpq Ut6JDX/25QZh2nzoKCPfPWlP395pw4A63ZMXb3J0vf5Eed/gEZHzjk3NQ4s0X8lt0Ggg iGt4IEOLrJ5o3UxzwuJJtJHsUiacdJrSqb75sZM/aaEHSj4rf/8jLPTXP2FrU+tDW7Q2 8tViKpbLP1psgQUTZ8lWIrHA28r8QzJVlx4xvsdpDirv32BEGwz2B+2fEMmyy0bhXwld MOOw== X-Gm-Message-State: AOJu0YygHyacwK7OJnnwWCC1Qc0XDFesAaXHg1XH3yzzXGE6Z9EbFkIL qgcHzfDLrXHZnLb09VuuSxFPLkaByJmN3R6P/IKLFEUsJljvyCcsaF/dIjkRKM1/fdo/Cp845t/ 6 X-Google-Smtp-Source: AGHT+IGJvFe6XqFhA1xaBxWHBA9Ghh+clmTanKzRnQWuoyED9yHlze9foDMZt4bqJnLnA9CxxQlUVA== X-Received: by 2002:a5d:6149:0:b0:33b:3bad:d3ee with SMTP id y9-20020a5d6149000000b0033b3badd3eemr1086210wrt.43.1707226177904; Tue, 06 Feb 2024 05:29:37 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCUm3OJ+YgXMLd6kJSMRIxqT4sbIwJIZMJrMnDjLXvXMlACoLZFW3VVz/n6UR6uveoXDeeEmUZtD2D6m5ViNreTKdhtzkc4= From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/13] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices Date: Tue, 6 Feb 2024 13:29:29 +0000 Message-Id: <20240206132931.38376-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206132931.38376-1-peter.maydell@linaro.org> References: <20240206132931.38376-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707226345299100004 Content-Type: text/plain; charset="utf-8" Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536 board. These are all simple devices that just need to be created and wired up. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 8c790313790..803ed0ffb5c 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -33,11 +33,16 @@ #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/or-irq.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" #include "hw/arm/bsa.h" #include "hw/char/cmsdk-apb-uart.h" +#include "hw/i2c/arm_sbcon_i2c.h" #include "hw/intc/arm_gicv3.h" +#include "hw/misc/unimp.h" +#include "hw/timer/cmsdk-apb-dualtimer.h" +#include "hw/watchdog/cmsdk-apb-watchdog.h" =20 /* Define the layout of RAM and ROM in a board */ typedef struct RAMInfo { @@ -97,6 +102,10 @@ struct MPS3RMachineState { CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX]; OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX]; OrIRQState uart_oflow; + CMSDKAPBWatchdog watchdog; + CMSDKAPBDualTimer dualtimer; + ArmSbconI2CState i2c[5]; + Clock *clk; }; =20 #define TYPE_MPS3R_MACHINE "mps3r" @@ -329,6 +338,9 @@ static void mps3r_common_init(MachineState *machine) MemoryRegion *sysmem =3D get_system_memory(); DeviceState *gicdev; =20 + mms->clk =3D clock_new(OBJECT(machine), "CLK"); + clock_set_hz(mms->clk, CLK_FRQ); + for (const RAMInfo *ri =3D mmc->raminfo; ri->name; ri++) { MemoryRegion *mr =3D mr_for_raminfo(mms, ri); memory_region_add_subregion(sysmem, ri->base, mr); @@ -421,6 +433,53 @@ static void mps3r_common_init(MachineState *machine) qdev_get_gpio_in(gicdev, combirq)); } =20 + for (int i =3D 0; i < 4; i++) { + /* CMSDK GPIO controllers */ + g_autofree char *s =3D g_strdup_printf("gpio%d", i); + create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000); + } + + object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, + TYPE_CMSDK_APB_WATCHDOG); + qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk); + sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, + qdev_get_gpio_in(gicdev, 0)); + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000); + + object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, + TYPE_CMSDK_APB_DUALTIMER); + qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk); + sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, + qdev_get_gpio_in(gicdev, 3)); + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1, + qdev_get_gpio_in(gicdev, 1)); + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2, + qdev_get_gpio_in(gicdev, 2)); + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000); + + for (int i =3D 0; i < ARRAY_SIZE(mms->i2c); i++) { + static const hwaddr i2cbase[] =3D {0xe0102000, /* Touch */ + 0xe0103000, /* Audio */ + 0xe0107000, /* Shield0 */ + 0xe0108000, /* Shield1 */ + 0xe0109000}; /* DDR4 EEPROM */ + g_autofree char *s =3D g_strdup_printf("i2c%d", i); + + object_initialize_child(OBJECT(mms), s, &mms->i2c[i], + TYPE_ARM_SBCON_I2C); + sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]); + if (i !=3D 2 && i !=3D 3) { + /* + * internal-only bus: mark it full to avoid user-created + * i2c devices being plugged into it. + */ + qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c")= ); + } + } + mms->bootinfo.ram_size =3D machine->ram_size; mms->bootinfo.board_id =3D -1; mms->bootinfo.loader_start =3D mmc->loader_start; --=20 2.34.1