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([102.35.208.160]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c211100b0040fc5460109sm1312756wml.35.2024.02.06.01.24.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 01:24:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707211498; x=1707816298; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b/g0mzC04szOUnabir1iLLohCVaDKcAp4uQzKj4Dxwg=; b=WqhZPq20rTP/4q7aSjt+/8odZ6p6q/mJAGXw1KAfYNrOxgzNwSbKutPk3UDbE4mXt0 jMXlMnA2RM/5qPVvZ1Ho5mOoGsAg51/LJEDNOldv5N8N9VtwieGZEFhyTn+POXL11InQ muE7JEwq1ZyPPWr6tAnNi6d62UzVBZ6e3Crue5zjVjPNYebUmE6vVAfRK/QCzAz7XJyl 5lHexawIi70xl2cjiOtu2kkFSUMLbFfYA3YIwvti9mvse9zLYsPJ2jkWtekTapA6jfKc E1KVh+OB6OUs6AQLijVyUBUd4+XdKlZxd7OqFQtKn45RfSPPT/s87xDcok6LmCAgEQNR O4Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707211498; x=1707816298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b/g0mzC04szOUnabir1iLLohCVaDKcAp4uQzKj4Dxwg=; b=vuAxKIVIiiIjvtXKHNdHhfAiv9b6+LB+qvMATOaBYMOC4KRR3DX4dOOGgkobUg8kg0 zz/VM0NQsypOzzb2bmEF+ibYpN1ymWUswSuxYLa1qaqCOzRGhQug/W3DKVJAXGkKolTt GWvXGA+auyjxgNfuXGst3ZPF3c7ewkV3T5lYtmdL5oEZTzHAnd6Biw89ve2kwPSrrokO xCfMdpAwRlyyAukwo9qWTpI6VxKC0zkekL2xOHJ1cUt0z4skEliWJqwqSTTHlRPMuplr 6fjUuC0flzltP4u/WGChrk2+JltzYtO5DZzeo0QvT0uuITetg1USyIO3CHWPULFJVPlt loag== X-Gm-Message-State: AOJu0YyJnABf4fnImQQ9Lu6Z1WeckSb+5r22BO7ivukGAjHNOMwjueRI +YN7EKvnIncoRNu9no8XDH5nBlu8lr1AOVbK/34iu/lpRUMgSkoYNVeM04cavjL8o7l5YYGvWEk lxJM= X-Google-Smtp-Source: AGHT+IH+8nT9xcnw94BA8stxbQa5xKFKrAuaY+V9Kp/tazUjFz7EkOk4Jru+sqD+K6ymiOxt+jl0jg== X-Received: by 2002:a05:600c:3b8b:b0:40f:df20:170e with SMTP id n11-20020a05600c3b8b00b0040fdf20170emr1176154wms.28.1707211498653; Tue, 06 Feb 2024 01:24:58 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCVkUoJtjxsYrrru7l6Q7fWujJ6IhxOQmpENemZpNSzhbD/MpcgbSBISnecs9TbnzgvStjswP8UBxvXneF3P3m8+vsuwgOAI4ynJcd3mn6VukHWzNAcsKzI8fDdWeaDl24vtzFZKllL6iFe2Jo2gBkWBxnJGnR8JSUpMXSkyMeOOTPlQDCIT/mEnXAkp4JbMRjdpt/sihwyJiqFejoACQDpDFsGMEAnVNHcKwspoIrqj1KI5vGnomL4qI1ovPq+qYDTh13wACY0unIqquP3pMX845aYrH+9D3kRCGpJXb4dPyxYq6VV4D70WiJPYpz1AN6MxKq0/ajGwWC8f+Qq+m4J1Nug++rjRfQ== From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Alexandre Iooss , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Mahmoud Mandour , Marcel Apfelbaum , Yanan Wang , Pierrick Bouvier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 07/17] plugins: implement inline operation relative to cpu_index Date: Tue, 6 Feb 2024 13:24:12 +0400 Message-ID: <20240206092423.3005995-8-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206092423.3005995-1-pierrick.bouvier@linaro.org> References: <20240206092423.3005995-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=pierrick.bouvier@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707211569545100003 Content-Type: text/plain; charset="utf-8" Instead of working on a fixed memory location, allow to address it based on cpu_index, an element size and a given offset. Result address: ptr + offset + cpu_index * element_size. With this, we can target a member in a struct array from a base pointer. Current semantic is not modified, thus inline operation still targets always the same memory location. Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- plugins/plugin.h | 2 +- accel/tcg/plugin-gen.c | 65 +++++++++++++++++++++++++++++++++++------- plugins/api.c | 3 +- plugins/core.c | 12 +++++--- 4 files changed, 65 insertions(+), 17 deletions(-) diff --git a/plugins/plugin.h b/plugins/plugin.h index fd93a372803..77ed10689ca 100644 --- a/plugins/plugin.h +++ b/plugins/plugin.h @@ -100,7 +100,7 @@ void plugin_register_vcpu_mem_cb(GArray **arr, enum qemu_plugin_mem_rw rw, void *udata); =20 -void exec_inline_op(struct qemu_plugin_dyn_cb *cb); +void exec_inline_op(struct qemu_plugin_dyn_cb *cb, int cpu_index); =20 int plugin_num_vcpus(void); =20 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index b37ce7683e6..68dee4c68d3 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -132,16 +132,28 @@ static void gen_empty_udata_cb_no_rwg(void) */ static void gen_empty_inline_cb(void) { + TCGv_i32 cpu_index =3D tcg_temp_ebb_new_i32(); + TCGv_ptr cpu_index_as_ptr =3D tcg_temp_ebb_new_ptr(); TCGv_i64 val =3D tcg_temp_ebb_new_i64(); TCGv_ptr ptr =3D tcg_temp_ebb_new_ptr(); =20 + tcg_gen_ld_i32(cpu_index, tcg_env, + -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); + /* pass an immediate !=3D 0 so that it doesn't get optimized away */ + tcg_gen_muli_i32(cpu_index, cpu_index, 0xdeadbeef); + tcg_gen_ext_i32_ptr(cpu_index_as_ptr, cpu_index); + tcg_gen_movi_ptr(ptr, 0); + tcg_gen_add_ptr(ptr, ptr, cpu_index_as_ptr); tcg_gen_ld_i64(val, ptr, 0); /* pass an immediate !=3D 0 so that it doesn't get optimized away */ tcg_gen_addi_i64(val, val, 0xdeadface); + tcg_gen_st_i64(val, ptr, 0); tcg_temp_free_ptr(ptr); tcg_temp_free_i64(val); + tcg_temp_free_ptr(cpu_index_as_ptr); + tcg_temp_free_i32(cpu_index); } =20 static void gen_empty_mem_cb(TCGv_i64 addr, uint32_t info) @@ -289,12 +301,37 @@ static TCGOp *copy_const_ptr(TCGOp **begin_op, TCGOp = *op, void *ptr) return op; } =20 +static TCGOp *copy_ld_i32(TCGOp **begin_op, TCGOp *op) +{ + return copy_op(begin_op, op, INDEX_op_ld_i32); +} + +static TCGOp *copy_ext_i32_ptr(TCGOp **begin_op, TCGOp *op) +{ + if (UINTPTR_MAX =3D=3D UINT32_MAX) { + op =3D copy_op(begin_op, op, INDEX_op_mov_i32); + } else { + op =3D copy_op(begin_op, op, INDEX_op_ext_i32_i64); + } + return op; +} + +static TCGOp *copy_add_ptr(TCGOp **begin_op, TCGOp *op) +{ + if (UINTPTR_MAX =3D=3D UINT32_MAX) { + op =3D copy_op(begin_op, op, INDEX_op_add_i32); + } else { + op =3D copy_op(begin_op, op, INDEX_op_add_i64); + } + return op; +} + static TCGOp *copy_ld_i64(TCGOp **begin_op, TCGOp *op) { if (TCG_TARGET_REG_BITS =3D=3D 32) { /* 2x ld_i32 */ - op =3D copy_op(begin_op, op, INDEX_op_ld_i32); - op =3D copy_op(begin_op, op, INDEX_op_ld_i32); + op =3D copy_ld_i32(begin_op, op); + op =3D copy_ld_i32(begin_op, op); } else { /* ld_i64 */ op =3D copy_op(begin_op, op, INDEX_op_ld_i64); @@ -330,6 +367,13 @@ static TCGOp *copy_add_i64(TCGOp **begin_op, TCGOp *op= , uint64_t v) return op; } =20 +static TCGOp *copy_mul_i32(TCGOp **begin_op, TCGOp *op, uint32_t v) +{ + op =3D copy_op(begin_op, op, INDEX_op_mul_i32); + op->args[2] =3D tcgv_i32_arg(tcg_constant_i32(v)); + return op; +} + static TCGOp *copy_st_ptr(TCGOp **begin_op, TCGOp *op) { if (UINTPTR_MAX =3D=3D UINT32_MAX) { @@ -395,18 +439,17 @@ static TCGOp *append_inline_cb(const struct qemu_plug= in_dyn_cb *cb, TCGOp *begin_op, TCGOp *op, int *unused) { - /* const_ptr */ - op =3D copy_const_ptr(&begin_op, op, cb->userp); - - /* ld_i64 */ + char *ptr =3D cb->userp; + size_t elem_size =3D 0; + size_t offset =3D 0; + op =3D copy_ld_i32(&begin_op, op); + op =3D copy_mul_i32(&begin_op, op, elem_size); + op =3D copy_ext_i32_ptr(&begin_op, op); + op =3D copy_const_ptr(&begin_op, op, ptr + offset); + op =3D copy_add_ptr(&begin_op, op); op =3D copy_ld_i64(&begin_op, op); - - /* add_i64 */ op =3D copy_add_i64(&begin_op, op, cb->inline_insn.imm); - - /* st_i64 */ op =3D copy_st_i64(&begin_op, op); - return op; } =20 diff --git a/plugins/api.c b/plugins/api.c index 15edad6769b..dedcbdfd30d 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -106,7 +106,8 @@ void qemu_plugin_register_vcpu_tb_exec_inline(struct qe= mu_plugin_tb *tb, void *ptr, uint64_t imm) { if (!tb->mem_only) { - plugin_register_inline_op(&tb->cbs[PLUGIN_CB_INLINE], 0, op, ptr, = imm); + plugin_register_inline_op(&tb->cbs[PLUGIN_CB_INLINE], + 0, op, ptr, imm); } } =20 diff --git a/plugins/core.c b/plugins/core.c index fd8604bcb79..863c2e64217 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -320,7 +320,8 @@ static struct qemu_plugin_dyn_cb *plugin_get_dyn_cb(GAr= ray **arr) =20 void plugin_register_inline_op(GArray **arr, enum qemu_plugin_mem_rw rw, - enum qemu_plugin_op op, void *ptr, + enum qemu_plugin_op op, + void *ptr, uint64_t imm) { struct qemu_plugin_dyn_cb *dyn_cb; @@ -476,9 +477,12 @@ void qemu_plugin_flush_cb(void) plugin_cb__simple(QEMU_PLUGIN_EV_FLUSH); } =20 -void exec_inline_op(struct qemu_plugin_dyn_cb *cb) +void exec_inline_op(struct qemu_plugin_dyn_cb *cb, int cpu_index) { - uint64_t *val =3D cb->userp; + char *ptr =3D cb->userp; + size_t elem_size =3D 0; + size_t offset =3D 0; + uint64_t *val =3D (uint64_t *)(ptr + offset + cpu_index * elem_size); =20 switch (cb->inline_insn.op) { case QEMU_PLUGIN_INLINE_ADD_U64: @@ -511,7 +515,7 @@ void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t va= ddr, vaddr, cb->userp); break; case PLUGIN_CB_INLINE: - exec_inline_op(cb); + exec_inline_op(cb, cpu->cpu_index); break; default: g_assert_not_reached(); --=20 2.43.0