From nobody Tue Nov 26 14:28:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1707124877; cv=none; d=zohomail.com; s=zohoarc; b=C1EeDDd72BhAqmCbZJ5XKZ/MhABEyG/I8vMdea6MY0WlYZ8OI3Bao2cT9CEW5+LrSfkpqK8CZyEBRbBPSxy7PkZoRwBLZ/D4P44/VJsWNbijRMFOmJyeCyTACWb2IZKWsTNQo5syyfCuMAEEpHcxuSE975yN/QnoLf25wp8SSWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1707124877; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Lhw2L1jqYjREvph9hPEoRJ/Obaw2GgkJkLNghjn7q0I=; b=SOeL9gERWguyCSSuw1F8O63qsP9pdlOT7/2OccMSFdgUzRKU9rgKwam8oMl+zR0hIPj5GXY5958GvRWvTuiTaraqPujvqFwUqWIo9f9EqgHi6sw9KMyrv94jdHHRG4zqt+TK91QeacdwYXkRI6JDS7H4Wc4fGAFIbhw90BRY3Cs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1707124877662634.1522084082914; Mon, 5 Feb 2024 01:21:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rWv9X-0004Ij-0y; Mon, 05 Feb 2024 04:20:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rWv9U-0004Hu-OP; Mon, 05 Feb 2024 04:20:32 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX02.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1rWv9T-0008Gf-3y; Mon, 05 Feb 2024 04:20:32 -0500 Received: from TWMBX02.aspeed.com (192.168.0.25) by TWMBX02.aspeed.com (192.168.0.25) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Feb 2024 17:14:17 +0800 Received: from twmbx02.aspeed.com (192.168.10.10) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 5 Feb 2024 17:14:17 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v0 1/2] aspeed: support uart controller both 0 and 1 base Date: Mon, 5 Feb 2024 17:14:13 +0800 Message-ID: <20240205091415.935686-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240205091415.935686-1-jamin_lin@aspeedtech.com> References: <20240205091415.935686-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Fail (TWMBX02.aspeed.com: domain of jamin_lin@aspeedtech.com does not designate 192.168.10.10 as permitted sender) receiver=TWMBX02.aspeed.com; client-ip=192.168.10.10; helo=twmbx02.aspeed.com; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX02.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1707124878651100003 Content-Type: text/plain; charset="utf-8" According to the design of ASPEED SOCS, the uart controller is 1 base for ast10x0, ast2600, ast2500 and ast2400. However, the uart controller is 0 base for ast2700. To support uart controller both 0 and 1 base, adds uasrt_bases parameter in AspeedSoCClass and set the default uart controller 1 base for ast10x0, astt2600, ast2500 and ast2400. From datasheet description ast2700: Base Address of UART0 =3D 0x14c33000 ast1030: Base Address of UART1 =3D 0x7e783000 ast2600: Base Address of UART1 =3D 0x1E78 3000 ast2500: Base Address of UART1 =3D 0x1E78 3000 Signed-off-by: Troy Lee Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 8 +++++--- hw/arm/aspeed_ast10x0.c | 1 + hw/arm/aspeed_ast2400.c | 2 ++ hw/arm/aspeed_ast2600.c | 1 + hw/arm/aspeed_soc_common.c | 4 ++-- include/hw/arm/aspeed_soc.h | 1 + 6 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 09b1e823ba..218b81298e 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -342,7 +342,7 @@ static void connect_serial_hds_to_uarts(AspeedMachineSt= ate *bmc) int uart_chosen =3D bmc->uart_chosen ? bmc->uart_chosen : amc->uart_de= fault; =20 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); - for (int i =3D 1, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, u= art++) { + for (int i =3D 1, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uar= t++) { if (uart =3D=3D uart_chosen) { continue; } @@ -1092,9 +1092,11 @@ static char *aspeed_get_bmc_console(Object *obj, Err= or **errp) { AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(bmc); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(obj); + int uart_chosen =3D bmc->uart_chosen ? bmc->uart_chosen : amc->uart_de= fault; =20 - return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1); + return g_strdup_printf("uart%d", uart_chosen - sc->uarts_base + 1); } =20 static void aspeed_set_bmc_console(Object *obj, const char *value, Error *= *errp) @@ -1114,7 +1116,7 @@ static void aspeed_set_bmc_console(Object *obj, const= char *value, Error **errp) error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts= _num); return; } - bmc->uart_chosen =3D ASPEED_DEV_UART1 + val - 1; + bmc->uart_chosen =3D sc->uarts_base + val - 1; } =20 static void aspeed_machine_class_props_init(ObjectClass *oc) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index c3b5116a6a..2634e0f654 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -436,6 +436,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *= klass, void *data) sc->wdts_num =3D 4; sc->macs_num =3D 1; sc->uarts_num =3D 13; + sc->uarts_base =3D ASPEED_DEV_UART1; sc->irqmap =3D aspeed_soc_ast1030_irqmap; sc->memmap =3D aspeed_soc_ast1030_memmap; sc->num_cpus =3D 1; diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 8829561bb6..95da85fee0 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -523,6 +523,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, void *data) sc->wdts_num =3D 2; sc->macs_num =3D 2; sc->uarts_num =3D 5; + sc->uarts_base =3D ASPEED_DEV_UART1; sc->irqmap =3D aspeed_soc_ast2400_irqmap; sc->memmap =3D aspeed_soc_ast2400_memmap; sc->num_cpus =3D 1; @@ -551,6 +552,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, void *data) sc->wdts_num =3D 3; sc->macs_num =3D 2; sc->uarts_num =3D 5; + sc->uarts_base =3D ASPEED_DEV_UART1; sc->irqmap =3D aspeed_soc_ast2500_irqmap; sc->memmap =3D aspeed_soc_ast2500_memmap; sc->num_cpus =3D 1; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 4ee32ea99d..f74561ecdc 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -666,6 +666,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *= oc, void *data) sc->wdts_num =3D 4; sc->macs_num =3D 4; sc->uarts_num =3D 13; + sc->uarts_base =3D ASPEED_DEV_UART1; sc->irqmap =3D aspeed_soc_ast2600_irqmap; sc->memmap =3D aspeed_soc_ast2600_memmap; sc->num_cpus =3D 2; diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 123a0c432c..3963436c3a 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -36,7 +36,7 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **e= rrp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); SerialMM *smm; =20 - for (int i =3D 0, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, u= art++) { + for (int i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uar= t++) { smm =3D &s->uart[i]; =20 /* Chardev property is set by the machine. */ @@ -58,7 +58,7 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **e= rrp) void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - int i =3D dev - ASPEED_DEV_UART1; + int i =3D dev - sc->uarts_base; =20 g_assert(0 <=3D i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 9d0af84a8c..ce2bb51682 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -140,6 +140,7 @@ struct AspeedSoCClass { int wdts_num; int macs_num; int uarts_num; + int uarts_base; const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; --=20 2.34.1