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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1707100851498100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/tcg/sme_helper.c | 32 +--------------- target/arm/tcg/sve_helper.c | 76 +++++++++---------------------------- 2 files changed, 20 insertions(+), 88 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 904bfdac43..b3e0ba9b29 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -459,14 +459,7 @@ void sme_ld1(CPUARMState *env, void *za, uint64_t *vg, sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, BP_MEM_READ, ra); =20 - /* - * Handle mte checks for all active elements. - * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. - */ - if (mtedesc) { - sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, - mtedesc, ra); - } + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, mtedesc, r= a); =20 flags =3D info.page[0].flags | info.page[1].flags; if (unlikely(flags !=3D 0)) { @@ -567,17 +560,10 @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t= *vg, CopyFn *cpy_fn) { uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); - int bit55 =3D extract64(addr, 55, 1); =20 /* Remove mtedesc from the normal sve descriptor. */ desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); =20 - /* Perform gross MTE suppression early. */ - if (!tbi_check(mtedesc, bit55) || - tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { - mtedesc =3D 0; - } - sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical, host_fn, tlb_fn, clr_fn, cpy_fn); } @@ -655,14 +641,7 @@ void sme_st1(CPUARMState *env, void *za, uint64_t *vg, sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, BP_MEM_WRITE, ra); =20 - /* - * Handle mte checks for all active elements. - * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. - */ - if (mtedesc) { - sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, - mtedesc, ra); - } + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, mtedesc, r= a); =20 flags =3D info.page[0].flags | info.page[1].flags; if (unlikely(flags !=3D 0)) { @@ -744,17 +723,10 @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t= *vg, target_ulong addr, sve_ldst1_tlb_fn *tlb_fn) { uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); - int bit55 =3D extract64(addr, 55, 1); =20 /* Remove mtedesc from the normal sve descriptor. */ desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); =20 - /* Perform gross MTE suppression early. */ - if (!tbi_check(mtedesc, bit55) || - tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { - mtedesc =3D 0; - } - sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical, host_fn, tlb_fn); } diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 6853f58c19..9fd469b00f 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5604,6 +5604,13 @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUA= RMState *env, int msize, uint32_t mtedesc, uintptr_t ra) { intptr_t mem_off, reg_off, reg_last; + int bit55 =3D extract64(addr, 55, 1); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(mtedesc, bit55) || + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { + return; + } =20 /* Process the page only if MemAttr =3D=3D Tagged. */ if (info->page[0].tagged) { @@ -5677,14 +5684,9 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const= target_ulong addr, sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz, BP_MEM_READ, retaddr); =20 - /* - * Handle mte checks for all active elements. - * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. - */ - if (mtedesc) { - sve_cont_ldst_mte_check(&info, env, vg, addr, 1 << esz, N << msz, - mtedesc, retaddr); - } + /* Handle mte checks for all active elements. */ + sve_cont_ldst_mte_check(&info, env, vg, addr, 1 << esz, N << msz, + mtedesc, retaddr); =20 flags =3D info.page[0].flags | info.page[1].flags; if (unlikely(flags !=3D 0)) { @@ -5794,17 +5796,10 @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, = target_ulong addr, sve_ldst1_tlb_fn *tlb_fn) { uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); - int bit55 =3D extract64(addr, 55, 1); =20 /* Remove mtedesc from the normal sve descriptor. */ desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); =20 - /* Perform gross MTE suppression early. */ - if (!tbi_check(mtedesc, bit55) || - tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { - mtedesc =3D 0; - } - sve_ldN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_= fn); } =20 @@ -5999,10 +5994,13 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, cons= t target_ulong addr, flags =3D info.page[0].flags; =20 /* - * Disable MTE checking if the Tagged bit is not set. Since TBI must - * be set within MTEDESC for MTE, !mtedesc =3D> !mte_active. + * Perform gross MTE suppression early. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. */ - if (!info.page[0].tagged) { + int bit55 =3D extract64(addr, 55, 1); + if (!info.page[0].tagged || + !tbi_check(mtedesc, bit55) || + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { mtedesc =3D 0; } =20 @@ -6150,17 +6148,10 @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, = target_ulong addr, sve_ldst1_tlb_fn *tlb_fn) { uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); - int bit55 =3D extract64(addr, 55, 1); =20 /* Remove mtedesc from the normal sve descriptor. */ desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); =20 - /* Perform gross MTE suppression early. */ - if (!tbi_check(mtedesc, bit55) || - tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { - mtedesc =3D 0; - } - sve_ldnfff1_r(env, vg, addr, desc, retaddr, mtedesc, esz, msz, fault, host_fn, tlb_fn); } @@ -6295,14 +6286,8 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, targe= t_ulong addr, sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz, BP_MEM_WRITE, retaddr); =20 - /* - * Handle mte checks for all active elements. - * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. - */ - if (mtedesc) { - sve_cont_ldst_mte_check(&info, env, vg, addr, 1 << esz, N << msz, - mtedesc, retaddr); - } + sve_cont_ldst_mte_check(&info, env, vg, addr, 1 << esz, N << msz, + mtedesc, retaddr); =20 flags =3D info.page[0].flags | info.page[1].flags; if (unlikely(flags !=3D 0)) { @@ -6404,17 +6389,10 @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, = target_ulong addr, sve_ldst1_tlb_fn *tlb_fn) { uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); - int bit55 =3D extract64(addr, 55, 1); =20 /* Remove mtedesc from the normal sve descriptor. */ desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); =20 - /* Perform gross MTE suppression early. */ - if (!tbi_check(mtedesc, bit55) || - tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { - mtedesc =3D 0; - } - sve_stN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_= fn); } =20 @@ -6596,12 +6574,6 @@ void sve_ld1_z_mte(CPUARMState *env, void *vd, uint6= 4_t *vg, void *vm, /* Remove mtedesc from the normal sve descriptor. */ desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); =20 - /* - * ??? TODO: For the 32-bit offset extractions, base + ofs cannot - * offset base entirely over the address space hole to change the - * pointer tag, or change the bit55 selector. So we could here - * examine TBI + TCMA like we do for sve_ldN_r_mte(). - */ sve_ld1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, esize, msize, off_fn, host_fn, tlb_fn); } @@ -6804,12 +6776,6 @@ void sve_ldff1_z_mte(CPUARMState *env, void *vd, uin= t64_t *vg, void *vm, /* Remove mtedesc from the normal sve descriptor. */ desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); =20 - /* - * ??? TODO: For the 32-bit offset extractions, base + ofs cannot - * offset base entirely over the address space hole to change the - * pointer tag, or change the bit55 selector. So we could here - * examine TBI + TCMA like we do for sve_ldN_r_mte(). - */ sve_ldff1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, esz, msz, off_fn, host_fn, tlb_fn); } @@ -7006,12 +6972,6 @@ void sve_st1_z_mte(CPUARMState *env, void *vd, uint6= 4_t *vg, void *vm, /* Remove mtedesc from the normal sve descriptor. */ desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); =20 - /* - * ??? TODO: For the 32-bit offset extractions, base + ofs cannot - * offset base entirely over the address space hole to change the - * pointer tag, or change the bit55 selector. So we could here - * examine TBI + TCMA like we do for sve_ldN_r_mte(). - */ sve_st1_z(env, vd, vg, vm, base, desc, retaddr, mtedesc, esize, msize, off_fn, host_fn, tlb_fn); } --=20 2.34.1