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d="scan'208";a="216352" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,240,1701158400"; d="scan'208";a="31378978" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org Cc: Zhenyu Wang , Zhuocheng Ding , Dapeng Mi , Yanting Jiang , Yongwei Ma , Zhao Liu Subject: [RFC 1/6] target/i386: Add support for save/load of ACPI thermal MSRs Date: Sat, 3 Feb 2024 17:30:49 +0800 Message-Id: <20240203093054.412135-2-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240203093054.412135-1-zhao1.liu@linux.intel.com> References: <20240203093054.412135-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=198.175.65.20; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.276, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1706951938602100006 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding The CPUID_ACPI (CPUID.0x01.edx[bit 22]) feature bit has been introduced as the TCG feature. Currently, based on KVM's ACPI emulation, add related ACPI support in QEMU. From SDM [1], ACPI feature means: "The ACPI flag (bit 22) of the CPUID feature flags indicates the presence of the IA32_THERM_STATUS, IA32_THERM_INTERRUPT, IA32_CLOCK_MODULATION MSRs, and the xAPIC thermal LVT entry." With the emulation of ACPI in KVM, add the support for save/load of ACPI thermal MSRs: MSR_IA32_THERM_CONTROL, MSR_IA32_THERM_INTERRUPT and MSR_IA32_THERM_STATUS. [1]: SDM, vol. 3B, section 15.8.4.1, Detection of Software Controlled Clock Modulation Extension. Tested-by: Yanting Jiang Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 25 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f0786e8b98f..e453b3f010e2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -526,6 +526,10 @@ typedef enum X86Seg { #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_UMWAIT_CONTROL 0xe1 =20 +#define MSR_IA32_THERM_CONTROL 0x0000019a +#define MSR_IA32_THERM_INTERRUPT 0x0000019b +#define MSR_IA32_THERM_STATUS 0x0000019c + #define MSR_IA32_VMX_BASIC 0x00000480 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 @@ -1758,6 +1762,11 @@ typedef struct CPUArchState { uint64_t msr_lbr_depth; LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; =20 + /* Per-VCPU thermal MSRs */ + uint64_t therm_control; + uint64_t therm_interrupt; + uint64_t therm_status; + /* exception/interrupt handling */ int error_code; int exception_is_int; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 76a66246eb72..3bf57b35bfcd 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -138,6 +138,7 @@ static bool has_msr_ucode_rev; static bool has_msr_vmx_procbased_ctls2; static bool has_msr_perf_capabs; static bool has_msr_pkrs; +static bool has_msr_therm; =20 static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -2455,6 +2456,11 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_PKRS: has_msr_pkrs =3D true; break; + case MSR_IA32_THERM_CONTROL: + case MSR_IA32_THERM_INTERRUPT: + case MSR_IA32_THERM_STATUS: + has_msr_therm =3D true; + break; } } } @@ -3302,6 +3308,11 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_virt_ssbd) { kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); } + if (has_msr_therm) { + kvm_msr_entry_add(cpu, MSR_IA32_THERM_CONTROL, env->therm_control); + kvm_msr_entry_add(cpu, MSR_IA32_THERM_INTERRUPT, env->therm_interr= upt); + kvm_msr_entry_add(cpu, MSR_IA32_THERM_STATUS, env->therm_status); + } =20 #ifdef TARGET_X86_64 if (lm_capable_kernel) { @@ -3774,6 +3785,11 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); env->tsc_valid =3D !runstate_is_running(); } + if (has_msr_therm) { + kvm_msr_entry_add(cpu, MSR_IA32_THERM_CONTROL, 0); + kvm_msr_entry_add(cpu, MSR_IA32_THERM_INTERRUPT, 0); + kvm_msr_entry_add(cpu, MSR_IA32_THERM_STATUS, 0); + } =20 #ifdef TARGET_X86_64 if (lm_capable_kernel) { @@ -4255,6 +4271,15 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info =3D msrs[i]= .data; break; + case MSR_IA32_THERM_CONTROL: + env->therm_control =3D msrs[i].data; + break; + case MSR_IA32_THERM_INTERRUPT: + env->therm_interrupt =3D msrs[i].data; + break; + case MSR_IA32_THERM_STATUS: + env->therm_status =3D msrs[i].data; + break; } } =20 --=20 2.34.1