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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k2-20020a05600c1c8200b0040fafd84095sm214735wms.41.2024.02.02.07.36.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 07:36:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706888214; x=1707493014; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/AEDkTvBGJa0LD/A6ZVlUM/YpBQnMTkyj2QgiWhIPMM=; b=hCSuD43E3N6nyJHj7OZK8jHJdGv4DM6drEgf5Du1YShBP2gzZPbIUyaVAV2K+Y47/W T/tU6JQzMXjHPO8N/Nb1H1Olahi7nV5uCssqHVepRWEAOCSFQaKF4pfZw9I7VhiZ5EnG i6enKlXwNBjgCw8N6cSuC27tfPJGk6vSr9yfgbY3y+LQBkWTNj69io42b+61q5REsNdM Qzxw2LoiJ76tXUnQOmH2BIqW60V+qwumQmJcOpjfs9HzFFA+g4U5jeT+S5Ai0MjrNZJT m3jc3FIoLtsz0/RdhdUcGnt41JsMxK3shvIAPp1viMlcvQYnzkS64exTvPe1SKuIj4Jd JYNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706888214; x=1707493014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/AEDkTvBGJa0LD/A6ZVlUM/YpBQnMTkyj2QgiWhIPMM=; b=J9QfqsX/OZrksfOXXhAih/vsVhr69Bz9tza5gcpfiieOTA1MiF9foP5Cq8nY8YxPUX 6cxEM7jRH9+quVzBa7K6T6QKl/6PuqrrQgAdf+AKYbhSV8XeLAIDQaU3soTLOfudqgXV 4ddh+mLIv2BGzusiicjJcIo7f0V9SB76XfqXxvTKuesMx9k5fgBzj4xnqVeDjvqjCHZd oQuVPuA1E2/wUq3S5Cy7CRmaGiavolktgkuU+NdX3qEpGrsymvyz+se7Hl3PCnW2jjGN diEeuVUhIgOZj4MRLKxQ7WgdBWCXegsXwVkQ66KDQtrMn1yLcRFayKHUmZFlXURFOBFo iOrQ== X-Gm-Message-State: AOJu0YwXZz/0mBdoM0y2cxKiwjoYQYdAOZpWRkG0EMiEXpoHV6pgspax QmnUuGHRwLx4ZOwkeDbjV1d9j8YPUeSESBMh7AcWNf6oLNKeEOUwkeW+ztuuriqEbw5YMvYae7W / X-Google-Smtp-Source: AGHT+IGbnZgifw5HkoPC3MH7mT3Xj7ys7qv4cvq630v55E3tk+a+VraiDs+LHRayC96PLBwhQiGY5A== X-Received: by 2002:a7b:cd97:0:b0:40e:f6f2:1706 with SMTP id y23-20020a7bcd97000000b0040ef6f21706mr6481637wmj.22.1706888213897; Fri, 02 Feb 2024 07:36:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/36] hw/net: GMAC Tx Implementation Date: Fri, 2 Feb 2024 15:36:34 +0000 Message-Id: <20240202153637.3710444-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202153637.3710444-1-peter.maydell@linaro.org> References: <20240202153637.3710444-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706888311913100003 Content-Type: text/plain; charset="utf-8" From: Nabih Estefan Diaz - Implementation of Transmit function for packets - Implementation for reading and writing from and to descriptors in memory for Tx Added relevant trace-events NOTE: This function implements the steps detailed in the datasheet for transmitting messages from the GMAC. Change-Id: Icf14f9fcc6cc7808a41acd872bca67c9832087e6 Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting Message-id: 20240131002800.989285-6-nabihestefan@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/net/npcm_gmac.c | 203 ++++++++++++++++++++++++++++++++++++++++++++ hw/net/trace-events | 2 + 2 files changed, 205 insertions(+) diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c index a3c626e1b83..1b71e2526e3 100644 --- a/hw/net/npcm_gmac.c +++ b/hw/net/npcm_gmac.c @@ -238,6 +238,37 @@ static int gmac_write_rx_desc(dma_addr_t addr, struct = NPCMGMACRxDesc *desc) return 0; } =20 +static int gmac_read_tx_desc(dma_addr_t addr, struct NPCMGMACTxDesc *desc) +{ + if (dma_memory_read(&address_space_memory, addr, desc, + sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->tdes0 =3D le32_to_cpu(desc->tdes0); + desc->tdes1 =3D le32_to_cpu(desc->tdes1); + desc->tdes2 =3D le32_to_cpu(desc->tdes2); + desc->tdes3 =3D le32_to_cpu(desc->tdes3); + return 0; +} + +static int gmac_write_tx_desc(dma_addr_t addr, struct NPCMGMACTxDesc *desc) +{ + struct NPCMGMACTxDesc le_desc; + le_desc.tdes0 =3D cpu_to_le32(desc->tdes0); + le_desc.tdes1 =3D cpu_to_le32(desc->tdes1); + le_desc.tdes2 =3D cpu_to_le32(desc->tdes2); + le_desc.tdes3 =3D cpu_to_le32(desc->tdes3); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + return 0; +} + static int gmac_rx_transfer_frame_to_buffer(uint32_t rx_buf_len, uint32_t *left_frame, uint32_t rx_buf_addr, @@ -459,6 +490,155 @@ static ssize_t gmac_receive(NetClientState *nc, const= uint8_t *buf, size_t len) return len; } =20 +static int gmac_tx_get_csum(uint32_t tdes1) +{ + uint32_t mask =3D TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(tdes1); + int csum =3D 0; + + if (likely(mask > 0)) { + csum |=3D CSUM_IP; + } + if (likely(mask > 1)) { + csum |=3D CSUM_TCP | CSUM_UDP; + } + + return csum; +} + +static void gmac_try_send_next_packet(NPCMGMACState *gmac) +{ + /* + * Comments about steps refer to steps for + * transmitting in page 384 of datasheet + */ + uint16_t tx_buffer_size =3D 2048; + g_autofree uint8_t *tx_send_buffer =3D g_malloc(tx_buffer_size); + uint32_t desc_addr; + struct NPCMGMACTxDesc tx_desc; + uint32_t tx_buf_addr, tx_buf_len; + uint16_t length =3D 0; + uint8_t *buf =3D tx_send_buffer; + uint32_t prev_buf_size =3D 0; + int csum =3D 0; + + /* steps 1&2 */ + if (!gmac->regs[R_NPCM_DMA_HOST_TX_DESC]) { + gmac->regs[R_NPCM_DMA_HOST_TX_DESC] =3D + NPCM_DMA_HOST_TX_DESC_MASK(gmac->regs[R_NPCM_DMA_TX_BASE_ADDR]= ); + } + desc_addr =3D gmac->regs[R_NPCM_DMA_HOST_TX_DESC]; + + while (true) { + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_TX_RUNNING_FETCHING_STATE); + if (gmac_read_tx_desc(desc_addr, &tx_desc)) { + qemu_log_mask(LOG_GUEST_ERROR, + "TX Descriptor @ 0x%x can't be read\n", + desc_addr); + return; + } + /* step 3 */ + + trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path, + desc_addr); + trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &tx_= desc, + tx_desc.tdes0, tx_desc.tdes1, tx_desc.tdes2, tx_desc.tdes3); + + /* 1 =3D DMA Owned, 0 =3D Software Owned */ + if (!(tx_desc.tdes0 & TX_DESC_TDES0_OWN)) { + qemu_log_mask(LOG_GUEST_ERROR, + "TX Descriptor @ 0x%x is owned by software\n", + desc_addr); + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_TU; + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_TX_SUSPENDED_STATE); + gmac_update_irq(gmac); + return; + } + + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_TX_RUNNING_READ_STATE); + /* Give the descriptor back regardless of what happens. */ + tx_desc.tdes0 &=3D ~TX_DESC_TDES0_OWN; + + if (tx_desc.tdes1 & TX_DESC_TDES1_FIRST_SEG_MASK) { + csum =3D gmac_tx_get_csum(tx_desc.tdes1); + } + + /* step 4 */ + tx_buf_addr =3D tx_desc.tdes2; + gmac->regs[R_NPCM_DMA_CUR_TX_BUF_ADDR] =3D tx_buf_addr; + tx_buf_len =3D TX_DESC_TDES1_BFFR1_SZ_MASK(tx_desc.tdes1); + buf =3D &tx_send_buffer[prev_buf_size]; + + if ((prev_buf_size + tx_buf_len) > sizeof(buf)) { + tx_buffer_size =3D prev_buf_size + tx_buf_len; + tx_send_buffer =3D g_realloc(tx_send_buffer, tx_buffer_size); + buf =3D &tx_send_buffer[prev_buf_size]; + } + + /* step 5 */ + if (dma_memory_read(&address_space_memory, tx_buf_addr, buf, + tx_buf_len, MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x= %x\n", + __func__, tx_buf_addr); + return; + } + length +=3D tx_buf_len; + prev_buf_size +=3D tx_buf_len; + + /* If not chained we'll have a second buffer. */ + if (!(tx_desc.tdes1 & TX_DESC_TDES1_SEC_ADDR_CHND_MASK)) { + tx_buf_addr =3D tx_desc.tdes3; + gmac->regs[R_NPCM_DMA_CUR_TX_BUF_ADDR] =3D tx_buf_addr; + tx_buf_len =3D TX_DESC_TDES1_BFFR2_SZ_MASK(tx_desc.tdes1); + buf =3D &tx_send_buffer[prev_buf_size]; + + if ((prev_buf_size + tx_buf_len) > sizeof(buf)) { + tx_buffer_size =3D prev_buf_size + tx_buf_len; + tx_send_buffer =3D g_realloc(tx_send_buffer, tx_buffer_siz= e); + buf =3D &tx_send_buffer[prev_buf_size]; + } + + if (dma_memory_read(&address_space_memory, tx_buf_addr, buf, + tx_buf_len, MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Failed to read packet @ 0x%x\n", + __func__, tx_buf_addr); + return; + } + length +=3D tx_buf_len; + prev_buf_size +=3D tx_buf_len; + } + if (tx_desc.tdes1 & TX_DESC_TDES1_LAST_SEG_MASK) { + net_checksum_calculate(tx_send_buffer, length, csum); + qemu_send_packet(qemu_get_queue(gmac->nic), tx_send_buffer, le= ngth); + trace_npcm_gmac_packet_sent(DEVICE(gmac)->canonical_path, leng= th); + buf =3D tx_send_buffer; + length =3D 0; + } + + /* step 6 */ + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_TX_RUNNING_CLOSING_STATE); + gmac_write_tx_desc(desc_addr, &tx_desc); + if (tx_desc.tdes1 & TX_DESC_TDES1_TX_END_RING_MASK) { + desc_addr =3D gmac->regs[R_NPCM_DMA_TX_BASE_ADDR]; + } else if (tx_desc.tdes1 & TX_DESC_TDES1_SEC_ADDR_CHND_MASK) { + desc_addr =3D tx_desc.tdes3; + } else { + desc_addr +=3D sizeof(tx_desc); + } + gmac->regs[R_NPCM_DMA_HOST_TX_DESC] =3D desc_addr; + + /* step 7 */ + if (tx_desc.tdes1 & TX_DESC_TDES1_INTERR_COMP_MASK) { + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_TI; + gmac_update_irq(gmac); + } + } +} + static void gmac_cleanup(NetClientState *nc) { /* Nothing to do yet. */ @@ -613,6 +793,29 @@ static void npcm_gmac_write(void *opaque, hwaddr offse= t, NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE); break; =20 + case A_NPCM_DMA_XMT_POLL_DEMAND: + /* We dont actually care about the value */ + gmac_try_send_next_packet(gmac); + break; + + case A_NPCM_DMA_CONTROL: + gmac->regs[offset / sizeof(uint32_t)] =3D v; + if (v & NPCM_DMA_CONTROL_START_STOP_TX) { + gmac_try_send_next_packet(gmac); + } else { + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_TX_STOPPED_STATE); + } + if (v & NPCM_DMA_CONTROL_START_STOP_RX) { + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE); + qemu_flush_queued_packets(qemu_get_queue(gmac->nic)); + } else { + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_RX_STOPPED_STATE); + } + break; + case A_NPCM_DMA_STATUS: /* Check that RO bits are not written to */ if (NPCM_DMA_STATUS_RO_MASK(v)) { diff --git a/hw/net/trace-events b/hw/net/trace-events index f91b1a4a3de..78efa2ec2cc 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -478,7 +478,9 @@ npcm_gmac_packet_desc_read(const char* name, uint32_t d= esc_addr) "%s: attempting npcm_gmac_packet_receive(const char* name, uint32_t len) "%s: RX packet le= ngth: 0x%04" PRIX32 npcm_gmac_packet_receiving_buffer(const char* name, uint32_t buf_len, uint= 32_t rx_buf_addr) "%s: Receiving into Buffer size: 0x%04" PRIX32 " at addre= ss 0x%04" PRIX32 npcm_gmac_packet_received(const char* name, uint32_t len) "%s: Reception f= inished, packet left: 0x%04" PRIX32 +npcm_gmac_packet_sent(const char* name, uint16_t len) "%s: TX packet sent!= , length: 0x%04" PRIX16 npcm_gmac_debug_desc_data(const char* name, void* addr, uint32_t des0, uin= t32_t des1, uint32_t des2, uint32_t des3)"%s: Address: %p Descriptor 0: 0x%= 04" PRIX32 " Descriptor 1: 0x%04" PRIX32 "Descriptor 2: 0x%04" PRIX32 " Des= criptor 3: 0x%04" PRIX32 +npcm_gmac_packet_tx_desc_data(const char* name, uint32_t tdes0, uint32_t t= des1) "%s: Tdes0: 0x%04" PRIX32 " Tdes1: 0x%04" PRIX32 =20 # npcm_pcs.c npcm_pcs_reg_read(const char *name, uint16_t indirect_access_baes, uint64_= t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 "= value: 0x%04" PRIx16 --=20 2.34.1