From nobody Tue Nov 26 15:43:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706888257; cv=none; d=zohomail.com; s=zohoarc; b=hKcvzUbELl3RxexZY8SOpLVoKJBrYRW6PtKiPHLskVCdtQGxm6bo1XCf8s7Fjs3MCfL6lcrC8igE0K9blGVuE1XF3M+MFK9+nBloqsayk1JLXKRWCXUh7H0AzzQQdGRzVuVqqwiqV9lxO9CN9mLamQFZ8kugg2xuZNaCCTqwOuw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706888257; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=N2NuZPUzpaElmLZXmhDdPQ/KTGn+fUluVp/XA+iMwnU=; b=gP9TIe6KiKNe2VlesQn/HYChVGWWMAbXTcSvvmlV2vbdKguC+kmpQppmXApahFIwnJaePnootCLkrO7jOXygw2nKIkZkRlVE9QsXg5KLdqR+P9JCYzg/PZS1+kOYYk+1Xprp/SG8w3Fl/Ds+D/QvrHB78r0R+x83vvgjQsKQHJw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706888257885828.3234726151502; Fri, 2 Feb 2024 07:37:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVvb9-0000Wa-Ls; Fri, 02 Feb 2024 10:36:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVvb6-0000Ni-E9 for qemu-devel@nongnu.org; Fri, 02 Feb 2024 10:36:56 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVvb4-0004Xr-PI for qemu-devel@nongnu.org; Fri, 02 Feb 2024 10:36:56 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40e80046246so5453885e9.1 for ; Fri, 02 Feb 2024 07:36:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k2-20020a05600c1c8200b0040fafd84095sm214735wms.41.2024.02.02.07.36.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 07:36:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706888212; x=1707493012; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=N2NuZPUzpaElmLZXmhDdPQ/KTGn+fUluVp/XA+iMwnU=; b=cssNInM2L+Z9U6BolKS9doMzY3z+NWkXnGE5pGGqmKdpx+yHdIPvHKZGLWV/Fht7AI enhnNnOcfKAOB2XagoZNMZ8hEkf7c4q/Z2mlcqNKfYzfV4ntV/9/gcQiLZL+JLln3pEd z8JeqUK5ZESruHJG2x1qi9/0kE2tLye0RMtc5/PgnDWtBhTt+d9S2IrMpv/eJ4l8C7vh /IuLKU1i1tYsXsMO+6Xvp+H2Y2N8NvLg/ATK+cVWnN/Lb7AK3JNfbHsx+eR3LoEkNOUq Iek7+nrtCMckUvRA7Vu+6urGhkv9wFj9OozpVep4a5DYhumki+zp+tpbYEOY0/5DmW+5 jJ8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706888212; x=1707493012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N2NuZPUzpaElmLZXmhDdPQ/KTGn+fUluVp/XA+iMwnU=; b=vnmLxWMLPWProJ1x5Q8Fjh2JWzu9jKDjQgpDbISPdLBjk2VgKRBX8B3pi5lFeGa42o 1Wp5KWjWXlLMiC/Y4ljKPJblT2x8R1E4ZI9HOkEmzq2HpsYXdvzsccZflCoFiIInPCUy Wlq6kMLApslwOQ6yLVw1W4j4r8FfHP8WwS0FzMXUBq7a+j3rw97hWBuJi3ZcYWwI5A99 qlEUhXOV+Fpj6OLXVT76LA4003RgHIjebKToHJxcQVrc58FGwwNPXm4g/D0V3gFXqohm BaLP6W+YKal9XU5pRP+5TnWmsIyTykjTFzqwHRuMgkBPR84oUfkJGYWVJSJhw5IN5d/0 4pxQ== X-Gm-Message-State: AOJu0Yxn+Ly/rqX4YluDI7aICvJAEE2iTus75EJTVGb9amP3v1JUwiPE id4FY6B9WjY6HyNoWFqB9NYgLqKrEuLA2reX1IoikPQOve/y/WZ0R6BS4eN0kzftc62iU5ZwTrs m X-Google-Smtp-Source: AGHT+IF6m2BSDq6wwrIBeeTFYdr5LdfI6dD60b7ElW8150FKyFUFeLYI1s4PQDo8cnnr2GoDoukwXA== X-Received: by 2002:a05:600c:458f:b0:40f:b2ba:b893 with SMTP id r15-20020a05600c458f00b0040fb2bab893mr2217169wmo.1.1706888212504; Fri, 02 Feb 2024 07:36:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/36] hw/arm: Add GMAC devices to NPCM7XX SoC Date: Fri, 2 Feb 2024 15:36:31 +0000 Message-Id: <20240202153637.3710444-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202153637.3710444-1-peter.maydell@linaro.org> References: <20240202153637.3710444-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706888259803100007 Content-Type: text/plain; charset="utf-8" From: Hao Wu Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565 Signed-off-by: Hao Wu Signed-off-by: Nabih Estefan Reviewed-by: Tyrone Ting Message-id: 20240131002800.989285-3-nabihestefan@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/npcm7xx.h | 2 ++ hw/arm/npcm7xx.c | 37 +++++++++++++++++++++++++++++++++++-- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 72c77220964..4e0d2101885 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -29,6 +29,7 @@ #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" #include "hw/net/npcm7xx_emc.h" +#include "hw/net/npcm_gmac.h" #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/ssi/npcm7xx_fiu.h" @@ -104,6 +105,7 @@ struct NPCM7xxState { OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; NPCM7xxEMCState emc[2]; + NPCMGMACState gmac[2]; NPCM7xxSDHCIState mmc; NPCMPSPIState pspi[2]; }; diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index e3243a520d8..d9dfdfcd51a 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -84,8 +84,10 @@ enum NPCM7xxInterrupt { NPCM7XX_UART1_IRQ, NPCM7XX_UART2_IRQ, NPCM7XX_UART3_IRQ, + NPCM7XX_GMAC1_IRQ =3D 14, NPCM7XX_EMC1RX_IRQ =3D 15, NPCM7XX_EMC1TX_IRQ, + NPCM7XX_GMAC2_IRQ, NPCM7XX_MMC_IRQ =3D 26, NPCM7XX_PSPI2_IRQ =3D 28, NPCM7XX_PSPI1_IRQ =3D 31, @@ -229,6 +231,12 @@ static const hwaddr npcm7xx_pspi_addr[] =3D { 0xf0201000, }; =20 +/* Register base address for each GMAC Module */ +static const hwaddr npcm7xx_gmac_addr[] =3D { + 0xf0802000, + 0xf0804000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -457,6 +465,10 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSP= I); } =20 + for (i =3D 0; i < ARRAY_SIZE(s->gmac); i++) { + object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMA= C); + } + object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); } =20 @@ -688,6 +700,29 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); } =20 + /* + * GMAC Modules. Cannot fail. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gmac_addr) !=3D ARRAY_SIZE(s->gma= c)); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->gmac) !=3D 2); + for (i =3D 0; i < ARRAY_SIZE(s->gmac); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->gmac[i]); + + /* + * The device exists regardless of whether it's connected to a QEMU + * netdev backend. So always instantiate it even if there is no + * backend. + */ + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_gmac_addr[i]); + int irq =3D i =3D=3D 0 ? NPCM7XX_GMAC1_IRQ : NPCM7XX_GMAC2_IRQ; + /* + * N.B. The values for the second argument sysbus_connect_irq are + * chosen to match the registration order in npcm7xx_emc_realize. + */ + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); + } + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip se= lects * specified, but this is a programming error. @@ -750,8 +785,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * = KiB); create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * = MiB); create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * = KiB); - create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * = KiB); - create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * = KiB); create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * = KiB); create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * = KiB); create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * = KiB); --=20 2.34.1