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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k2-20020a05600c1c8200b0040fafd84095sm214735wms.41.2024.02.02.07.36.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 07:36:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706888209; x=1707493009; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=I3JpUFeuz8JEq3ye2dfNhThlFiBiIs8gN5QDvvRsL0g=; b=yNXji4qhm1LYe/mx45v3f+8lbclOs/8GtxzTw3kGUrwI2zZdqDVbDr0V2ysr6NQWnt F+fQ9sSQEXrqNN6AgYICLai2lMI+ehcLsYHfLffJixza2TC64vFjm9gaFNB49uF1KNo9 a6tXkDLxlhefk0rDpl7J2QIlbRMW/Zj9dOZd/JY6Pb7afWV1+ixHTa+Goqj9XIGloFAf YE2P0HlscVCfHF/rdzBwRBjHZEDpqN7T+2xW550rmn3l1NW82ES6JrtZc+Wr9TUjIxj6 +2J967BPZ/oh+OJ5Xkpf5kbCF/f/Hc8IktqxAi0WRL3k4ehMAPwjEOcwu28es0pm054u g+HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706888209; x=1707493009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I3JpUFeuz8JEq3ye2dfNhThlFiBiIs8gN5QDvvRsL0g=; b=ECCQ+v1z6qInZne2SD/meu8U2DBAik799M+AxOKexXSCFYTyHc/ZEGpo9NqqUXwU0f TxHkRpFcJT8MCxiFzbVNEu5tYhGM7SSRuq8mmi0DzSNMSwG2JvARGY/DzI2zeqhbC3MD CIwd+B7QFDtoydU3MbTJDNWbDpV5mO2tYrRrD4K0QxOOfZjOMJu9IM0lD01jiGRmJKSp A0ddT5Aq8i9qTK7WsvTwLJ/hRjnJyQVTRQ0k66XqvDVFQhc67fFXXUcqJin/Fb3fAoIn Fx/1LQm5+9XhiQypnNpf6Z0JwBcdxlA+5PoaEQM3XPGzVroYzIWqoMY+mnxLa+9x9qpI e9uA== X-Gm-Message-State: AOJu0YztOvwu/2FxG9exCEOTW+HcPxSwDs7rNbtkYjr8coOkHhTcxAhI /sukfBsMFL8XFITQhyQA1I5BvxToSlair+wjmuc3/9HL1ZewQioCB/YRhkvLSLT+EwSgW3MyqvP + X-Google-Smtp-Source: AGHT+IHvijeREeWEfwB+wQk6zlSaRP9lSiacdiK9UNU9yVjX7IrcRZQDylI9zwfv1nq3G7xPTo7cLA== X-Received: by 2002:a05:600c:524e:b0:40e:f222:9e52 with SMTP id fc14-20020a05600c524e00b0040ef2229e52mr1677514wmb.40.1706888209179; Fri, 02 Feb 2024 07:36:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/36] hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors Date: Fri, 2 Feb 2024 15:36:24 +0000 Message-Id: <20240202153637.3710444-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202153637.3710444-1-peter.maydell@linaro.org> References: <20240202153637.3710444-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706888287866100001 From: Manos Pitsidianakis Tracing DPRINTFs to stderr might not be desired. A developer that relies on trace events should be able to opt-in to each trace event and rely on QEMU's log redirection, instead of stderr by default. This commit converts DPRINTFs in this file that are used for tracing into trace events. DPRINTFs that report guest errors are logged with LOG_GUEST_ERROR.# Signed-off-by: Manos Pitsidianakis Reviewed-by: Alex Benn=C3=A9e Message-id: 39db71dd87bf2007cf7812f3d91dde53887f1f2f.1706544115.git.manos.p= itsidianakis@linaro.org Signed-off-by: Peter Maydell --- hw/arm/strongarm.c | 82 ++++++++++++++++++++++++++++----------------- hw/arm/trace-events | 3 ++ 2 files changed, 55 insertions(+), 30 deletions(-) diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 7fd99a0f144..823b4931b0a 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -46,8 +46,7 @@ #include "qemu/log.h" #include "qom/object.h" #include "target/arm/cpu-qom.h" - -//#define DEBUG +#include "trace.h" =20 /* TODO @@ -66,12 +65,6 @@ - Enhance UART with modem signals */ =20 -#ifdef DEBUG -# define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) -#else -# define DPRINTF(format, ...) do { } while (0) -#endif - static struct { hwaddr io_base; int irq; @@ -151,8 +144,9 @@ static uint64_t strongarm_pic_mem_read(void *opaque, hw= addr offset, case ICPR: return s->pending; default: - printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n", - __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad register offset 0x"HWADDR_FMT_plx"\n", + __func__, offset); return 0; } } @@ -173,8 +167,9 @@ static void strongarm_pic_mem_write(void *opaque, hwadd= r offset, s->int_idle =3D (value & 1) ? 0 : ~0; break; default: - printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n", - __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad register offset 0x"HWADDR_FMT_plx"\n", + __func__, offset); break; } strongarm_pic_update(s); @@ -333,7 +328,9 @@ static uint64_t strongarm_rtc_read(void *opaque, hwaddr= addr, ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); default: - printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad rtc register read 0x"HWADDR_FMT_plx"\n", + __func__, addr); return 0; } } @@ -375,7 +372,9 @@ static void strongarm_rtc_write(void *opaque, hwaddr ad= dr, break; =20 default: - printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad rtc register write 0x"HWADDR_FMT_plx"\n", + __func__, addr); } } =20 @@ -556,12 +555,12 @@ static uint64_t strongarm_gpio_read(void *opaque, hwa= ddr offset, =20 case GPSR: /* GPIO Pin-Output Set registers */ qemu_log_mask(LOG_GUEST_ERROR, - "strongarm GPIO: read from write only register GPSR\= n"); + "%s: read from write only register GPSR\n", __func__= ); return 0; =20 case GPCR: /* GPIO Pin-Output Clear registers */ qemu_log_mask(LOG_GUEST_ERROR, - "strongarm GPIO: read from write only register GPCR\= n"); + "%s: read from write only register GPCR\n", __func__= ); return 0; =20 case GRER: /* GPIO Rising-Edge Detect Enable registers */ @@ -581,7 +580,9 @@ static uint64_t strongarm_gpio_read(void *opaque, hwadd= r offset, return s->status; =20 default: - printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad gpio read offset 0x"HWADDR_FMT_plx"\n", + __func__, offset); } =20 return 0; @@ -626,7 +627,9 @@ static void strongarm_gpio_write(void *opaque, hwaddr o= ffset, break; =20 default: - printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad write offset 0x"HWADDR_FMT_plx"\n", + __func__, offset); } } =20 @@ -782,7 +785,9 @@ static uint64_t strongarm_ppc_read(void *opaque, hwaddr= offset, return s->ppfr | ~0x7f001; =20 default: - printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad ppc read offset 0x"HWADDR_FMT_plx "\n", + __func__, offset); } =20 return 0; @@ -817,7 +822,9 @@ static void strongarm_ppc_write(void *opaque, hwaddr of= fset, break; =20 default: - printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad ppc write offset 0x"HWADDR_FMT_plx"\n", + __func__, offset); } } =20 @@ -1029,8 +1036,13 @@ static void strongarm_uart_update_parameters(StrongA= RMUARTState *s) s->char_transmit_time =3D (NANOSECONDS_PER_SECOND / speed) * frame_si= ze; qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); =20 - DPRINTF(stderr, "%s speed=3D%d parity=3D%c data=3D%d stop=3D%d\n", s->= chr->label, - speed, parity, data_bits, stop_bits); + trace_strongarm_uart_update_parameters((s->chr.chr ? + s->chr.chr->label : "NULL") ?: + "NULL", + speed, + parity, + data_bits, + stop_bits); } =20 static void strongarm_uart_rx_to(void *opaque) @@ -1164,7 +1176,9 @@ static uint64_t strongarm_uart_read(void *opaque, hwa= ddr addr, return s->utsr1; =20 default: - printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad uart register read 0x"HWADDR_FMT_plx"\n", + __func__, addr); return 0; } } @@ -1221,7 +1235,9 @@ static void strongarm_uart_write(void *opaque, hwaddr= addr, break; =20 default: - printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad uart register write 0x"HWADDR_FMT_plx"\n", + __func__, addr); } } =20 @@ -1434,7 +1450,7 @@ static uint64_t strongarm_ssp_read(void *opaque, hwad= dr addr, return 0xffffffff; } if (s->rx_level < 1) { - printf("%s: SSP Rx Underrun\n", __func__); + trace_strongarm_ssp_read_underrun(); return 0xffffffff; } s->rx_level--; @@ -1443,7 +1459,9 @@ static uint64_t strongarm_ssp_read(void *opaque, hwad= dr addr, strongarm_ssp_fifo_update(s); return retval; default: - printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad ssp register read 0x"HWADDR_FMT_plx"\n", + __func__, addr); break; } return 0; @@ -1458,8 +1476,8 @@ static void strongarm_ssp_write(void *opaque, hwaddr = addr, case SSCR0: s->sscr[0] =3D value & 0xffbf; if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { - printf("%s: Wrong data size: %i bits\n", __func__, - (int)SSCR0_DSS(value)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Wrong data size: %i bits\n= ", + __func__, (int)SSCR0_DSS(value)); } if (!(value & SSCR0_SSE)) { s->sssr =3D 0; @@ -1471,7 +1489,9 @@ static void strongarm_ssp_write(void *opaque, hwaddr = addr, case SSCR1: s->sscr[1] =3D value & 0x2f; if (value & SSCR1_LBM) { - printf("%s: Attempt to use SSP LBM mode\n", __func__); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Attempt to use SSP LBM mode\n", + __func__); } strongarm_ssp_fifo_update(s); break; @@ -1509,7 +1529,9 @@ static void strongarm_ssp_write(void *opaque, hwaddr = addr, break; =20 default: - printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad ssp register write 0x"HWADDR_FMT_plx"\n", + __func__, addr); break; } } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index cdc1ea06a81..7c569432150 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -55,3 +55,6 @@ smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifi= er node for iommu mr=3D%s smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, = uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d vmi= d=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64 =20 +# strongarm.c +strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" +strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.34.1