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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k2-20020a05600c1c8200b0040fafd84095sm214735wms.41.2024.02.02.07.36.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 07:36:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706888205; x=1707493005; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=k/KtHzrgDY0sCTDgXF5o6E+FF2YFpOZCP9knTxPgJ0Q=; b=OYvMROQjjs3MpNyxgBHKaxUFfA3t0wqxT5RCFiT1oC+NH+XEnfm9Z2AAiOHAvd8loQ 2ydkWp49xM8KXZkh+uxbIpJf1cex5fAlYV/Jr0XA7Sq/LqxaEJKF74aOJCmP498NNh5t gUKhTPJcXfLXXTMFkrz3iSAuVQflHgo//NUlYNkkE4mrQASK5Q9iZMaD5nqBYWpIArIw vLGyZIgURuLUtfLM1LvY4FHOPeaioCZolhg7ASZg/5Q6WVVDzb3XoFWdfzJ1Lj4Xh+ja zXsPKelzhhHcY8xEXMcSlko30NLVgIShSaHBLkPeeqAzBU9QpiUtnLPMrNL2hfy3MHuD wcVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706888205; x=1707493005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k/KtHzrgDY0sCTDgXF5o6E+FF2YFpOZCP9knTxPgJ0Q=; b=Qwv1UuHqaGHI5YveoQqh3BmmIJ3U+FPv0N69gVU2M+alZ9OnwzAJPVGYIXWQCZU1Bz +QFV3oxg5tJn5ekWbRkDJTnqvivztw5/oB9ShJKhxIYURrvk+x6WGF7QZTXZ/Ij6OcOU PqvS8ifyVsALhLk0QZd6hubWmnB7Z75mz+ipf30Qj0g1KmFEHw4K6hLIPBJVEcya5U9D 8Zgcn0BuiQ9s3hi1kPairzDpfjKvaWGti92TvyOycfBd+AluCn7AObAdkkdb26Adcy4g Sd/xmFh2HTX6q922ukmnlYVa0SKdX75h2kUFIDt8/bbQ8N2AawZPd1BK46RQu01vkECm flCQ== X-Gm-Message-State: AOJu0Yx6FMdGAeo/D0G63BkxtZZImQeKG+ZaSHhATeBHrU4qQaen1Mc5 Yls/mNIQhmYAVIsUy2KfTZEpP/B7I9S5H3GQqdwHacrWccwKZhhnpm6+6j8kFWn9/E7+H8QZ6HB B X-Google-Smtp-Source: AGHT+IHeOh3s3Xg4ln4UilKZ4jGUifVQlH91Og2dl4Xcg6A8CrUCYTKOPcEOOvcsKYKMQWPo0tE0kQ== X-Received: by 2002:a05:6512:b8c:b0:511:3865:2dda with SMTP id b12-20020a0565120b8c00b0051138652ddamr1424311lfv.2.1706888204997; Fri, 02 Feb 2024 07:36:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/36] hw/arm/exynos: Add missing QOM parent for CPU cores Date: Fri, 2 Feb 2024 15:36:14 +0000 Message-Id: <20240202153637.3710444-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202153637.3710444-1-peter.maydell@linaro.org> References: <20240202153637.3710444-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706888235476100001 From: Philippe Mathieu-Daud=C3=A9 QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20240129151828.59544-2-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 6c428d8eeb4..57c77b140c2 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -556,6 +556,7 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) for (n =3D 0; n < EXYNOS4210_NCPUS; n++) { Object *cpuobj =3D object_new(ARM_CPU_TYPE_NAME("cortex-a9")); =20 + object_property_add_child(OBJECT(s), "cpu[*]", cpuobj); /* By default A9 CPUs have EL3 enabled. This board does not curre= ntly * support EL3 so the CPU EL3 property is disabled before realizat= ion. */ --=20 2.34.1