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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853074; x=1707457874; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jy1cBvfDLGAIWcltw0Maq00BzyfiZt9oMrUlfaadwKU=; b=LBjTOy5ikY2/djP5ISxrOBfPFYbCdDw48wh9gMVfk8S7r5jicd/8yuWa56S36RrNwe yo9E7AFLSwF2RytiBbl8bx9mWwuGWqZzR4I8xm3OGHvcqCN1NB8mfPbJAClpyR/WZIu0 /A39aLYJ6U+5YLs6zAop43QFE+ONOZk1iyT5KFhCB7myXRoh6fCm35OY9A5qa22ki/6e GH0ynIjS+reEhmO0/2xH4y/D4COUt5t9zn9Y8hlJaQhPOrG/MjM3Li9cpra0gBdOr8W7 VgsTxKnDyrwyLH62IwYYuiRUGw+JAVQCMFUxotS2sLzilEipIaCozG3wOT1tSo0/2Dmu I6pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853074; x=1707457874; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jy1cBvfDLGAIWcltw0Maq00BzyfiZt9oMrUlfaadwKU=; b=YFAf1XEfOVlU0CQTh2GmJPDNs7V+hRqe8THqTrFRC4jLGh/AY4+wyQAHrHFHzUN5TV SwtPCGM0gpKxKba55Rqm/0V+YGBQBRnXbW3aimmqg/TasZZ0m5saNDcD9HZzNcIIXvEg +XDdFnJFmsKlDKFjrw4+wVAfRqJm2QhyusSAAb74Pggd8NpV1aFrJ/n+YbvQhvxhe5nD RDf6WWwi1I8JlYbl1M4W1E9mRb8l6QLWU/HxHKIpMjmG4YLgu5XoPhBDKxsfqXjSTGRt YbKlF3hkXwljAaQOFZyK6oTjElx//Z7dbg358OrtIL2JG+fQL5ZFAnqVSBoJVXQbLthd Jj8g== X-Gm-Message-State: AOJu0YxB0vrrAJPXZJ9kykDYc40cDdF7VqcYgEcG1iD7xbb4OcqnK8XH ckFItKSRLjLqsgXlJrJs/Vayd/vWHrkNcCj1tT9/IBYozJocmyMyvTRVBD4sKYZflRK7MFflxsu 1jlA= X-Google-Smtp-Source: AGHT+IExzi4Z2GHdQFOxjfytLf0AFnpRMbjhUfPtJW2s8AbVJuAvzrZR4eufimEoD01zx4eck9OgFg== X-Received: by 2002:a05:6a00:1407:b0:6df:f634:4f83 with SMTP id l7-20020a056a00140700b006dff6344f83mr1777323pfu.2.1706853074021; Thu, 01 Feb 2024 21:51:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 15/57] target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill Date: Fri, 2 Feb 2024 15:49:54 +1000 Message-Id: <20240202055036.684176-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853421524100001 Rather than adjust env->hflags so that the value computed by cpu_mmu_index() changes, compute the mmu_idx that we want directly and pass it down. Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/cpu.h | 4 +++- target/mips/tcg/sysemu/tlb_helper.c | 32 ++++++++++++----------------- 2 files changed, 16 insertions(+), 20 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1163a71f3c..3ba8dccd2d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1242,12 +1242,14 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState = *env); * MMU modes definitions. We carefully match the indices with our * hflags layout. */ +#define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 2 +#define MMU_ERL_IDX 3 =20 static inline int hflags_mmu_index(uint32_t hflags) { if (hflags & MIPS_HFLAG_ERL) { - return 3; /* ERL */ + return MMU_ERL_IDX; } else { return hflags & MIPS_HFLAG_KSU; } diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index 4ede904800..b715449114 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -623,7 +623,7 @@ static uint64_t get_tlb_entry_layout(CPUMIPSState *env,= uint64_t entry, static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, int directory_index, bool *huge_page, bool *hgpg_directory_hit, uint64_t *pw_entrylo0, uint64_t *pw_entrylo1, - unsigned directory_shift, unsigned leaf_shift) + unsigned directory_shift, unsigned leaf_shift, int ptw_mmu_idx) { int dph =3D (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; int psn =3D (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; @@ -638,8 +638,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, uint64_t w =3D 0; =20 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { /* wrong base address */ return 0; } @@ -666,8 +665,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, *pw_entrylo0 =3D entry; } if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_= LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return 0; } if (!get_pte(env, vaddr2, leafentry_size, &entry)) { @@ -690,7 +688,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, } =20 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, - int mmu_idx) + int ptw_mmu_idx) { int gdw =3D (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; int udw =3D (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; @@ -776,7 +774,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D goffset; switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -793,7 +791,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D uoffset; switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -810,7 +808,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D moffset; switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -825,8 +823,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, /* Leaf Level Page Table - First half of PTE pair */ vaddr |=3D ptoffset0; if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return false; } if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { @@ -838,8 +835,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, /* Leaf Level Page Table - Second half of PTE pair */ vaddr |=3D ptoffset1; if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return false; } if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { @@ -944,12 +940,10 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, * Memory reads during hardware page table walking are performed * as if they were kernel-mode load instructions. */ - int mode =3D (env->hflags & MIPS_HFLAG_KSU); - bool ret_walker; - env->hflags &=3D ~MIPS_HFLAG_KSU; - ret_walker =3D page_table_walk_refill(env, address, mmu_idx); - env->hflags |=3D mode; - if (ret_walker) { + int ptw_mmu_idx =3D (env->hflags & MIPS_HFLAG_ERL ? + MMU_ERL_IDX : MMU_KERNEL_IDX); + + if (page_table_walk_refill(env, address, ptw_mmu_idx)) { ret =3D get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); if (ret =3D=3D TLBRET_MATCH) { --=20 2.34.1