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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853067; x=1707457867; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RnZ4z27JEwUmWsta9h8D7ESSdJL0MTSBNlDpkb4+YYg=; b=w2b6fwvy2N2HepF4d2jx/bQiNQH4RXRm5SMFpgFrfbbvSlT6VarHBLEBsmFsELt0ks 6xRJ8aUPlPgNjtLTgx4cH14mcAGkD9/2Ji8G4CXx1gAKQw9l/UmwF2q1J55p4n2GIKGv LobTArNHn+kGnm7huoR0gC12KVhijblPrg09FLviKN/NjZOfsv0NDivlq2FunA07Y6FN ltU7HzWWH66su+AT+H8TvO+IbIj89BBqTnI3+AnY6aaMcCWgrmKfN1xj8QqXnkcTNaB9 BquBU2ys7kuz2ifsBuTb31obsxr6KGIAwEzw75ewt1cJD8PzbOFebzBiY7Kyf1NUZyJa OhIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853067; x=1707457867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RnZ4z27JEwUmWsta9h8D7ESSdJL0MTSBNlDpkb4+YYg=; b=uO97eO4IBgJtDT7FbPN7SwmyFF64wFxLKTrlL8hi2MQBa13tcqIoYjIMbgPOFPk3Lp Pq4dzMzjfvbt2dsOKlcJ+0HF1YY38oHgnUV4VJU16V7qQfeoy3ulZdtYAlNNwA/78jiH mdEoDwDd7mQSlrMXPhS9q8A57rHS55ChhvIHaoVMnmKaz67sWzwr6ywHGHHfKjr/HgHm 70XcQpif2q8ocgJyDN7q4GonMZR/M/ONZcT3W4R72+cWwV3drGiNisObNRSqQD6WQtgV ekFAb6QHPjV4mnjpTIZE4KXch+kbEtN3aGhvp1fUhofQqsdk4fzLmsL3/t4ki/EjwGr6 rqDA== X-Gm-Message-State: AOJu0YywlbPWosRZk742zs+5ZMyAsFeWgT4J8MqM+wPft22lKQd73t+U yu3exNSzPn+PcEqOJHmMx5byOYA8VLMEtx75mIwb+wNZHH6a+KXSVUJHSsrVoreVjEgBkQf1GTH +cTA= X-Google-Smtp-Source: AGHT+IGxhQIgc72bx7QdzDED5VEYIXtelv1gx6eKgmlS55EKFPreYPXuBDrZUO9suVobJPDRgxOZAw== X-Received: by 2002:a05:6a00:1491:b0:6dd:892f:e2a6 with SMTP id v17-20020a056a00149100b006dd892fe2a6mr1821005pfu.23.1706853067761; Thu, 01 Feb 2024 21:51:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 12/57] target/loongarch: Rename MMU_IDX_* Date: Fri, 2 Feb 2024 15:49:51 +1000 Message-Id: <20240202055036.684176-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853108381100005 The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. Rename to match generic code. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 8 ++++---- target/loongarch/cpu.c | 2 +- target/loongarch/tcg/tlb_helper.c | 4 ++-- target/loongarch/tcg/translate.c | 2 +- target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 5dfcfeb3a4..47fd110e81 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -404,15 +404,15 @@ struct LoongArchCPUClass { */ #define MMU_PLV_KERNEL 0 #define MMU_PLV_USER 3 -#define MMU_IDX_KERNEL MMU_PLV_KERNEL -#define MMU_IDX_USER MMU_PLV_USER -#define MMU_IDX_DA 4 +#define MMU_KERNEL_IDX MMU_PLV_KERNEL +#define MMU_USER_IDX MMU_PLV_USER +#define MMU_DA_IDX 4 =20 int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY - return MMU_IDX_USER; + return MMU_USER_IDX; #else return loongarch_cpu_mmu_index(env_cpu(env), ifetch); #endif diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index cbecc63213..139acfe373 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -382,7 +382,7 @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); } - return MMU_IDX_DA; + return MMU_DA_IDX; } =20 static void loongarch_la464_initfn(Object *obj) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 449043c68b..65ffbef08e 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -188,8 +188,8 @@ static int get_physical_address(CPULoongArchState *env,= hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type, int mmu_idx) { - int user_mode =3D mmu_idx =3D=3D MMU_IDX_USER; - int kernel_mode =3D mmu_idx =3D=3D MMU_IDX_KERNEL; + int user_mode =3D mmu_idx =3D=3D MMU_USER_IDX; + int kernel_mode =3D mmu_idx =3D=3D MMU_KERNEL_IDX; uint32_t plv, base_c, base_v; int64_t addr_high; uint8_t da =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 235515c629..58674cb268 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -125,7 +125,7 @@ static void loongarch_tr_init_disas_context(DisasContex= tBase *dcbase, if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { ctx->mem_idx =3D ctx->plv; } else { - ctx->mem_idx =3D MMU_IDX_DA; + ctx->mem_idx =3D MMU_DA_IDX; } =20 /* Bound the number of insns to execute to those left on the page. */ diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe= t/loongarch/tcg/insn_trans/trans_privileged.c.inc index 01d457212b..7e4ec93edb 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -323,7 +323,7 @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr= _d) =20 static void check_mmu_idx(DisasContext *ctx) { - if (ctx->mem_idx !=3D MMU_IDX_DA) { + if (ctx->mem_idx !=3D MMU_DA_IDX) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; } --=20 2.34.1