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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:50:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853043; x=1707457843; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PumilLrArPZLdXkeLrIHmsOcHqv6B2J+77pEclyDIK0=; b=mHeK0vW7SeG8bGL4TCIaLkRjZpA1J6cqgtRKNOCopJ8UsPmpe1y4bSlXG3ONzYhfVX 99M8yeuzulnov4Xv4s7OoIOrQofevMLO3dg7/4iiyFf4uwrTmjQH4HCzT/VJA0BY8h2A g/iJaXQVXcVGnsALy0V/PIVcO8F5Zh9rO91E5+XjNx9euAm/sci1M08F97TP/ggOWJS5 HkPQydM0rA400wO2AxRi6e+JZ2tMNmYzwrPbhJcU/yAfHqIqWbMsk8gL2f9N2puj0BDn 38GXkNHGAzOnelTpZBmCZubhfFqCxxCbUhEjHUuZBHmnW3DBaTRE5Ep4iC7gzhZzTigt kLWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853043; x=1707457843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PumilLrArPZLdXkeLrIHmsOcHqv6B2J+77pEclyDIK0=; b=KIz6OXBUw0D7n4h+AzPGoGhOZuFZ5CKU8nOhiZhJGbG4P4IMgqB45qilZ+AEwtl4Ia 1MPrZPlPVAYeTzey1VMVOqirK7mqdFUqsIiJgq9fB1nd6Z4wtpCPg9jADKZPcGjiaSCw 6m6dyq7WvmPAwbqD8wYHnxuhvCOl11f3T3cs8wpzdNje4P3MuNy+4jbZzQtW9L2oo1XS JKdwzcokcKKLkY64pKng5W/3t+xqNPtuWQBKZ2GwEd0bruQMQtSXwjeGsivojl8c3a/n iKWrOW977CWiUadxoTXuADm2mCukkmYoXdEOCi5HU6O16x5tszXIciHeMOKC1toQUHe2 wxdg== X-Gm-Message-State: AOJu0Yw2aAXgN1400DUNCh1lWFy9+tQ2aqCqfruBaHsvwqHoYCG8tbZS rQu1vMDTLqA3R8Mw+MUCOx2D9AelezTJBAQMGkewLzW170GRssgQqyAOj2Z6IkPAvT1go9kzfpj /KRU= X-Google-Smtp-Source: AGHT+IGt9MSIOmTnSEMnO5y+U1uG5LUD6cC88TAg/GGOpyBEn6suXyGW4OBxpAnuc8ZvFRxZvXvTxw== X-Received: by 2002:a05:6808:4493:b0:3bd:e392:fab9 with SMTP id eq19-20020a056808449300b003bde392fab9mr1737515oib.38.1706853042852; Thu, 01 Feb 2024 21:50:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/57] include/hw/core: Add mmu_index to CPUClass Date: Fri, 2 Feb 2024 15:49:39 +1000 Message-Id: <20240202055036.684176-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853170450100003 To be used after all targets have populated the hook. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2c284d6397..4385ce54c9 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,6 +103,8 @@ struct SysemuCPUOps; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. + * @mmu_index: Callback for choosing softmmu mmu index; + * may be used internally by memory_rw_debug without TCG. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: @@ -150,6 +152,7 @@ struct CPUClass { void (*parse_features)(const char *typename, char *str, Error **errp); =20 bool (*has_work)(CPUState *cpu); + int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853093; cv=none; d=zohomail.com; s=zohoarc; b=cNlI/d5LUeObt904KBOIBYidnsAJn1DfFHU5oNrYjNe8uYbqF2u37o9plUQNTNKqwGx1Q7TX5xY46AJBgOZlTkWvoqK3DP4rfzL1SWELzusE5vUsDh159GA/9T7Zel/uQss4sCwNGgaT+rX6rl8tCjv4l+yqOhJgWVCf85XUvxg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853093; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ih9kNFtuKNhrUdysAgLO3jiT9TTjcwOFp1g4b3mJWUA=; b=UwD1ukbg8ctZ6lPDXM/Fox/4ccXYpJyYzVQgKEHIVpkH8M6l8QBV7a9nzUhpqWvJrVh+jw0z8Na6gk4RFh88c6zn+f64pgzZS4nvqU2CTvqkABVmgco/YOARArt+eCvlYFe6/u6L81Ua8v0DAjgapAVobIZjMSgeaFDdngO5GEU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853093747494.82599235702935; Thu, 1 Feb 2024 21:51:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmRv-00014K-5e; Fri, 02 Feb 2024 00:50:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmRt-00012n-QO for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:50:49 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmRs-0001bf-Co for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:50:49 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6de2735151cso1229867b3a.1 for ; Thu, 01 Feb 2024 21:50:48 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:50:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853047; x=1707457847; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ih9kNFtuKNhrUdysAgLO3jiT9TTjcwOFp1g4b3mJWUA=; b=QgTHM0Vpf1nqXtlqGFg5C7e4Br9r1TKRpZOw9aXUsKNrai2KIVbkEFgsuPAS68soK0 7p0wlEEWUObisjPvHWkwhe7+AS1bCSxHjwZGSDwW3Kgdz+KDpfwjbFcXP6/9kWnyVBWb 2DQwMLyG5OT40aBxZ45MxHXR9CYIxsK2SnqmZLX11SQn8DyouDJ8Z5TDZo1KFM5u3oT8 4bKcTesW5WneG0e+Dtx4DtAzhtgqObHas4eSs0BlZ5PTwY8BCLFO+4n4Pvz/M7hmqpt7 rEGKyCVKwn/Iwjh5FYes0ckMDXobWEPInET5C6I8gHj5SygyARYoxIFLro44n2EbHsVt 5NRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853047; x=1707457847; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ih9kNFtuKNhrUdysAgLO3jiT9TTjcwOFp1g4b3mJWUA=; b=Q+72sb3ojkyei69D85Wep8zKL20nuNrwGKdWJAOXytN8kv5II0jb3j2Z3wLXYIrNNs dqEXWToXgifZ3/LLagor8yYQuudYpDUMPVyc6+9XS8eJlzSYjgzr89nXXfMcxgAv9PCa LxUKzVyhNi2WTjukU1ZZ6f6NuAXOGf8nhy1LnCBqqxwYDYdj7G3Q1oq2eZ9IHSn1h6is haqR7/LzNoOlIRlT+sMXkbRFBG3j1w0rHhjTipOhPjCtlHVBIJBuKKZThaWpW63VUcXh zjwtAGkV/7P8lzuFyManh3LStf2iOyvw2RlP+7pwRQbQ7OMIrpDTvWsZJD8Zlw7QOnEA h1+Q== X-Gm-Message-State: AOJu0YyDB9Sb7fQZqU8kMfz/h4UgqeJfGelj/5/lWGr7pTN1P7DNn+Zf KAA/drOOpXHHwgQFuY90PXJjYA/8jxelSUjMReeU7r8+xXMc3hlYLRtb+1sDJRWEpIGdTKMGODu neAw= X-Google-Smtp-Source: AGHT+IE76fgrLlqvPpz21UuQ/1qw55eyXaHWy7qxfQ78uUHMw6z/hAHi2P1wjaeLZbBlbGpQDlS/Sw== X-Received: by 2002:a05:6a00:1407:b0:6df:f634:4f83 with SMTP id l7-20020a056a00140700b006dff6344f83mr1776559pfu.2.1706853046932; Thu, 01 Feb 2024 21:50:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/57] target/alpha: Split out alpha_env_mmu_index Date: Fri, 2 Feb 2024 15:49:41 +1000 Message-Id: <20240202055036.684176-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853094506100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 7 ++++++- target/alpha/translate.c | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce806587ca..3beff2738a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -389,7 +389,7 @@ enum { =20 #define TB_FLAG_UNALIGN (1u << 1) =20 -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +static inline int alpha_env_mmu_index(CPUAlphaState *env) { int ret =3D env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_= IDX; if (env->flags & ENV_FLAG_PAL_MODE) { @@ -398,6 +398,11 @@ static inline int cpu_mmu_index(CPUAlphaState *env, bo= ol ifetch) return ret; } =20 +static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +{ + return alpha_env_mmu_index(env); +} + enum { IR_V0 =3D 0, IR_T0 =3D 1, diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 134eb7225b..4b464f8651 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2875,7 +2875,7 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) int64_t bound; =20 ctx->tbflags =3D ctx->base.tb->flags; - ctx->mem_idx =3D cpu_mmu_index(env, false); + ctx->mem_idx =3D alpha_env_mmu_index(env); ctx->implver =3D env->implver; ctx->amask =3D env->amask; =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853124; cv=none; d=zohomail.com; s=zohoarc; b=IsmWVXVQF3w9edW/3vq0glOEuOQ/sVa7QKQp7Ub8RJQLKJw+2780s9dhvujK/4xMptfpCX0c7AdnxN6J/Y/P5XILwWlAQiOcIlJJCWerroNWV+h660Hse51E080LmgUexmbzwWwRudnYEJHnneghYtwTmSuR44t4w4xPTHSzyuA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853124; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9zf0HbVX8gvUwqhja+dnyq/HEcNPpSpWkMmM6ss3Zow=; b=EjBCFrv3yxdLRmJqMyqIOR3qiaQ49U6bbjR4hgH4TLGjcGUjwSMPlmtbHIoA2sNs02GuZPE576CX5/5ZbBAKqnUzqlRGcsWloUWTJfYO6ViwohBlQpOv+mEs2iBl9M0XZSokkB8PICs//6XjRsYR8Iy0quuZF88aYnxYmizOarU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853124552335.6643540261913; Thu, 1 Feb 2024 21:52:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmRy-00016o-F5; Fri, 02 Feb 2024 00:50:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmRx-000165-5i for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:50:53 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmRu-0001cQ-Ay for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:50:52 -0500 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-5d8df34835aso320193a12.0 for ; Thu, 01 Feb 2024 21:50:49 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:50:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853049; x=1707457849; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9zf0HbVX8gvUwqhja+dnyq/HEcNPpSpWkMmM6ss3Zow=; b=YnnonL4dfILdH4WWHiCC2VZVGZvGDqCOIwfg68aklOHD7NUwrWiJcuIhiaXkh05QSk W97giU4a8gm5jc3LbHyvLpekTqosExf45HurDMcXViVVB7Xe+8VbaT3RbkPrwzEyZ9Bj XyeA2ukjRRHg+6ITpAMyVJgDSwIu5aJG5Ne1r6OE7iq5isUPG5VAZ7/D3gsXQE57OYZZ VpWN0cPZ8g8LqrxvBBC7XAteSWP82tZLqVvOIAEorOZy7LLLOqPNEPL2z7MKQbFL/fDY Ceotu180+Jt/xo4rQhhylXzfP5+rzjECJ20P7cc9iauZY/aRvOC2WaPs0YRjZ2Q/0LIq +DvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853049; x=1707457849; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853126517100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index de705c3703..bf70173a25 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -64,6 +64,11 @@ static bool alpha_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_MCHK); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853094512100002 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 +++++ target/arm/helper.c | 2 +- target/arm/tcg/helper-a64.c | 4 ++-- target/arm/tcg/mte_helper.c | 18 +++++++++--------- target/arm/tcg/sve_helper.c | 8 ++++---- target/arm/tcg/tlb_helper.c | 2 +- 6 files changed, 22 insertions(+), 17 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 71d6c70bf3..fc337fe40e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -40,6 +40,11 @@ #define BANK_HYP 6 #define BANK_MON 7 =20 +static inline int arm_env_mmu_index(CPUARMState *env) +{ + return EX_TBFLAG_ANY(env->hflags, MMUIDX); +} + static inline bool excp_is_internal(int excp) { /* Return true if this exception number represents a QEMU-internal diff --git a/target/arm/helper.c b/target/arm/helper.c index 945d8571a6..b0488caf40 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7841,7 +7841,7 @@ static void dccvap_writefn(CPUARMState *env, const AR= MCPRegInfo *opaque, uint64_t vaddr_in =3D (uint64_t) value; uint64_t vaddr =3D vaddr_in & ~(dline_size - 1); void *haddr; - int mem_idx =3D cpu_mmu_index(env, false); + int mem_idx =3D arm_env_mmu_index(env); =20 /* This won't be crossing page boundaries */ haddr =3D probe_read(env, vaddr, dline_size, mem_idx, GETPC()); diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 198b975f20..ebaa7f00df 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -856,7 +856,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) tbii =3D EX_TBFLAG_A64(env->hflags, TBII); if ((tbii >> extract64(new_pc, 55, 1)) & 1) { /* TBI is enabled. */ - int core_mmu_idx =3D cpu_mmu_index(env, false); + int core_mmu_idx =3D arm_env_mmu_index(env); if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) { new_pc =3D sextract64(new_pc, 0, 56); } else { @@ -925,7 +925,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) */ int blocklen =3D 4 << env_archcpu(env)->dcz_blocksize; uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); void *mem; =20 /* diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index ffb8ea1c34..d971b81370 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -291,7 +291,7 @@ static int load_tag1(uint64_t ptr, uint8_t *mem) =20 uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uint8_t *mem; int rtag =3D 0; =20 @@ -311,7 +311,7 @@ static void check_tag_aligned(CPUARMState *env, uint64_= t ptr, uintptr_t ra) { if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, - cpu_mmu_index(env, false), ra); + arm_env_mmu_index(env), ra); g_assert_not_reached(); } } @@ -344,7 +344,7 @@ typedef void stg_store1(uint64_t, uint8_t *, int); static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, uintptr_t ra, stg_store1 store1) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uint8_t *mem; =20 check_tag_aligned(env, ptr, ra); @@ -371,7 +371,7 @@ void HELPER(stg_parallel)(CPUARMState *env, uint64_t pt= r, uint64_t xt) =20 void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uintptr_t ra =3D GETPC(); =20 check_tag_aligned(env, ptr, ra); @@ -381,7 +381,7 @@ void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt, uintptr_t ra, stg_store1 store1) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); int tag =3D allocation_tag_from_addr(xt); uint8_t *mem1, *mem2; =20 @@ -429,7 +429,7 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t p= tr, uint64_t xt) =20 void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uintptr_t ra =3D GETPC(); int in_page =3D -(ptr | TARGET_PAGE_MASK); =20 @@ -445,7 +445,7 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) =20 uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uintptr_t ra =3D GETPC(); int gm_bs =3D env_archcpu(env)->gm_blocksize; int gm_bs_bytes =3D 4 << gm_bs; @@ -505,7 +505,7 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) =20 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); uintptr_t ra =3D GETPC(); int gm_bs =3D env_archcpu(env)->gm_blocksize; int gm_bs_bytes =3D 4 << gm_bs; @@ -555,7 +555,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint6= 4_t val) void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) { uintptr_t ra =3D GETPC(); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); int log2_dcz_bytes, log2_tag_bytes; intptr_t dcz_bytes, tag_bytes; uint8_t *mem; diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index f006d152cc..bce4295d28 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5481,7 +5481,7 @@ bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFa= ult fault, CPUARMState *env, target_ulong addr, MMUAccessType access_type, uintptr_t retaddr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D arm_env_mmu_index(env); int mem_off =3D info->mem_off_first[0]; bool nofault =3D fault =3D=3D FAULT_NO; bool have_work =3D true; @@ -6529,7 +6529,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D arm_env_mmu_index(env); const intptr_t reg_max =3D simd_oprsz(desc); const int scale =3D simd_data(desc); ARMVectorReg scratch; @@ -6715,7 +6715,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D arm_env_mmu_index(env); const intptr_t reg_max =3D simd_oprsz(desc); const int scale =3D simd_data(desc); const int esize =3D 1 << esz; @@ -6920,7 +6920,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D arm_env_mmu_index(env); const intptr_t reg_max =3D simd_oprsz(desc); const int scale =3D simd_data(desc); void *host[ARM_MAX_VQ * 4]; diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5477c7fb7d..885bf4ec14 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -281,7 +281,7 @@ void helper_exception_pc_alignment(CPUARMState *env, ta= rget_ulong pc) { ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Alignment }; int target_el =3D exception_target_el(env); - int mmu_idx =3D cpu_mmu_index(env, true); + int mmu_idx =3D arm_env_mmu_index(env); uint32_t fsc; =20 env->exception.vaddress =3D pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853533; cv=none; d=zohomail.com; s=zohoarc; b=hShSfLKhGWO+LSGiiF+CwMgFBMb9O5LEjTrDJwhjzwJHQf9uUALxMc09San9hFBY/gf+5yyFdOwv/15LIIzj53c9E3e1Wv9PcJmzKJw2flpHuSzS2KVLXRvvY4PsfvHxEchNVdXTMwTBxyepm7EzfBkKBxhcdd5wJehklPe0BXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853533; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853533804100013 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6a96b245f2..1f9ea622bd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -133,6 +133,11 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_EXITTB); } =20 +static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return arm_env_mmu_index(cpu_env(cs)); +} + void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { @@ -2497,6 +2502,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D arm_cpu_class_by_name; cc->has_work =3D arm_cpu_has_work; + cc->mmu_index =3D arm_cpu_mmu_index; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; cc->get_pc =3D arm_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853154; cv=none; d=zohomail.com; s=zohoarc; b=lVikzZ1OW1SY1jH53HewL0FTp9TGWtJVRD8ZXh7oSevVkw1aSoO9rbIVi5mwJ1Gcx/F+nqHXAfYhUlKRcuQZbuKDKIa8fkx5fVwrLhjnnyg6UEsCWyAIhHh7fO4wZfX0tZPtwxdKNqH7iZa7t8VjAl2g9u1gnbuQ1avCH6dovk4= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:50:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853055; x=1707457855; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yw2P2PO5VlSnBjLMn3wVhUzylUVudEj93tNb1F3kdv4=; b=pX4WnSb6Uv0oECWgI4HaxBazN6LiMv9a1dufowbwDmp2NJJwhraUeBooeWpmVb+kAy p0Cq5WBoNQCKhSEHehxDgEmubMBbxLZq4l/U+po3W4+KNvg70YFIDxdd5yjcJciN+KP8 1c5KcBqi5ttie4rF57K+8c+c1MjcLlH2XZFUza/YSI7N//G9xh3+0GUsRGONjRHdzY6I GUTqQovrzAMFCfvfyFhrgBvW3v00XvYZkJOCL5sW9RYpPMlOqfm8O9ZjmYYuq6ASCYw1 D89Nuo+NJNTcl7ruoH6q1p0rn4e6qYLQnUnz8sAyqv7pfXHQPOQaDD+p3zADxNXAIXKz 6dLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853055; x=1707457855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yw2P2PO5VlSnBjLMn3wVhUzylUVudEj93tNb1F3kdv4=; b=c03chpBQT+5wZeC99p+vs82o5pqcXxAznPuNuDG83XQF1FYQnzvfp5fCZWXUWiSG3y D0r0+mImxhuRNfoe/he4u8kdglNZnkuhQIz3ODiDD03wkv4dukWOIszcmjzGwykpxoyI FxYE3JG2bysxBaQyusMul/7cC+uESBYYtqTmc4H5DUqB2+C1ph1JLJOrEhD2XWbq7Cxe m+7zFtxrMWgByi6zxTTYPc1KBpzYp/zEsqhfFZePWxXoxcgKlpfFpzk9BsDIyvjdDiX4 kdFuDkTn4gZ2vDcwMB8ojzdwdFgbpSdegOYFOAew0q/+6yltPLhHzH3VFgMuCIcurox6 PbLw== X-Gm-Message-State: AOJu0YzIRIgs6V7f37ZBGDBReosNGxcSNjI1I8K9lkmCPPE5OxLGfBVE 9OoR0rzaJ4d98R9/2y6ShRUbiL4IH7PYrU6o0aojJNC+iXgucQ/R/Gi4LCaS3I15bbX40c8Bb8h WdB0= X-Google-Smtp-Source: AGHT+IEmi7bqO5BtyUgH0b09kOqLL5QNdC3uwyMB8SjraD1jYMWz/A7KqVPZ5qWyTSJsbZImYC3SJQ== X-Received: by 2002:a05:6a20:dda2:b0:19c:9af5:a472 with SMTP id kw34-20020a056a20dda200b0019c9af5a472mr4862414pzb.62.1706853055179; Thu, 01 Feb 2024 21:50:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 06/57] target/avr: Populate CPUClass.mmu_index Date: Fri, 2 Feb 2024 15:49:45 +1000 Message-Id: <20240202055036.684176-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853154440100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/avr/cpu.h | 4 +--- target/avr/cpu.c | 6 ++++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7d5dd42575..4595c6bb18 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,9 +184,7 @@ static inline void set_avr_feature(CPUAVRState *env, in= t feature) env->features |=3D (1U << feature); } =20 -#define cpu_mmu_index avr_cpu_mmu_index - -static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) +static inline int cpu_mmu_index(CPUAVRState *env, bool ifetch) { return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 1c68748b24..a40f445af2 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -50,6 +50,11 @@ static bool avr_cpu_has_work(CPUState *cs) && cpu_interrupts_enabled(env); } =20 +static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; +} + static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -236,6 +241,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->class_by_name =3D avr_cpu_class_by_name; =20 cc->has_work =3D avr_cpu_has_work; + cc->mmu_index =3D avr_cpu_mmu_index; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->get_pc =3D avr_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853101; cv=none; d=zohomail.com; s=zohoarc; b=AJVFFDlti70pCUt1XiCSV998SQa4lNXbpksxFslc3/FxQhYhVsBzgIcECG355+wi9387yZkJpw3MXPUakOkRJ/ix0HEx83tRl9C0Zkx2J9Sw64YHzGu/I+ArYCAbCrEW+aTjRwrZsnUAEIIeQ79WW09yv/EZ8zkdQsZxF/lRo18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853101; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2CLw1/Gtxm8k7/hVT+/nUKJ1+Eret/bnzWs0hJWPqBU=; b=hfObiiQkJvWNhviZTk1tIFpWv52S7EFpAM7Err2XJH/Nz1Jgr/Umc4TnPfkS0k1ibiIOmTqCS1xRG/2I8VTs5Kl5xDt4cdp0okTIbMlYUyC8FYRIyuP83N7xxPAI9fRCmIfcuE3EOW9F5npLvei3+U/1D5/atDpZrWh0gveM2O8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853101777113.48512252218313; Thu, 1 Feb 2024 21:51:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmS5-0001BL-Sx; Fri, 02 Feb 2024 00:51:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmS4-0001Ad-3a for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:00 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmS2-0001ej-DN for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:50:59 -0500 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-5d7005ea1d0so316617a12.1 for ; Thu, 01 Feb 2024 21:50:58 -0800 (PST) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/cris/translate.c | 14 +++++--------- target/cris/translate_v10.c.inc | 6 ++---- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index ee1402a9a3..7acea29a01 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -94,6 +94,7 @@ typedef struct DisasContext { =20 CRISCPU *cpu; target_ulong pc, ppc; + int mem_index; =20 /* Decoder. */ unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc= ); @@ -1008,37 +1009,31 @@ static inline void cris_prepare_jmp (DisasContext *= dc, unsigned int type) =20 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch =3D=3D 1) { cris_store_direct_jmp(dc); } =20 - tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEUQ); + tcg_gen_qemu_ld_i64(dst, addr, dc->mem_index, MO_TEUQ); } =20 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,=20 unsigned int size, int sign) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch =3D=3D 1) { cris_store_direct_jmp(dc); } =20 - tcg_gen_qemu_ld_tl(dst, addr, mem_index, + tcg_gen_qemu_ld_tl(dst, addr, dc->mem_index, MO_TE + ctz32(size) + (sign ? MO_SIGN : 0)); } =20 static void gen_store (DisasContext *dc, TCGv addr, TCGv val, unsigned int size) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch =3D=3D 1) { @@ -1055,7 +1050,7 @@ static void gen_store (DisasContext *dc, TCGv addr, T= CGv val, return; } =20 - tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size)); + tcg_gen_qemu_st_tl(val, addr, dc->mem_index, MO_TE + ctz32(size)); =20 if (dc->flags_x) { cris_evaluate_flags(dc); @@ -2971,6 +2966,7 @@ static void cris_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) dc->cpu =3D env_archcpu(env); dc->ppc =3D pc_start; dc->pc =3D pc_start; + dc->mem_index =3D cpu_mmu_index(env, false); dc->flags_uptodate =3D 1; dc->flags_x =3D tb_flags & X_FLAG; dc->cc_x_uptodate =3D 0; diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.= inc index 6df599fdce..73fc27c15d 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -91,8 +91,6 @@ static void gen_store_v10_conditional(DisasContext *dc, T= CGv addr, TCGv val, static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, unsigned int size) { - int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch =3D=3D 1) { @@ -101,11 +99,11 @@ static void gen_store_v10(DisasContext *dc, TCGv addr,= TCGv val, =20 /* Conditional writes. */ if (dc->flags_x) { - gen_store_v10_conditional(dc, addr, val, size, mem_index); + gen_store_v10_conditional(dc, addr, val, size, dc->mem_index); return; } =20 - tcg_gen_qemu_st_tl(val, addr, mem_index, ctz32(size) | MO_TE); + tcg_gen_qemu_st_tl(val, addr, dc->mem_index, ctz32(size) | MO_TE); } =20 =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853549; cv=none; d=zohomail.com; s=zohoarc; b=DwX+dEd9XpwCxgKFOzNAsO7gav/Vx+YzPy28wXyTTJ41CMUW7mBVZbBk6n2m1U9MxpJNtQ3J6Hgf56eQvbJrtez7visImHur88FaI8Aq6ew9OL7vZScUJ77gQX4olVdPlV97wDZREyYbdoHkn2/7iIFGUc7kVcSpmggbYWHNrmE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853549; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Wl6EjnJRU6kShqd/niIm85pRxEWSBZnxx+3jHXQP+xk=; b=ioEvxL5NPD2xJ9wbm/bdaPx7nnJ0COyftuyVLKklMnJNImS4mYWsALH7AicDzMb/EQZunCJgd0+w+0VXUMB8o7uhPfKzdD9bx1C82b/aZ0fjr8ulQH+NHic6KcrXP9s7v2ff9oSVzKVHG+Q3UKk1Ro8e/VQCQu8To+cQAJIxk2o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853549551278.93841850780916; Thu, 1 Feb 2024 21:59:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmS7-0001Bc-4C; Fri, 02 Feb 2024 00:51:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmS5-0001BE-OJ for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:01 -0500 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmS4-0001fa-Cc for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:01 -0500 Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-3bda4bd14e2so1399379b6e.2 for ; Thu, 01 Feb 2024 21:51:00 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853549844100005 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/cris/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6349148b65..163fb05d58 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -56,6 +56,11 @@ static bool cris_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 +static int cris_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return !!(cpu_env(cs)->pregs[PR_CCS] & U_FLAG); +} + static void cris_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); @@ -274,6 +279,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; + cc->mmu_index =3D cris_cpu_mmu_index; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; cc->get_pc =3D cris_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853155; cv=none; d=zohomail.com; s=zohoarc; b=YrLLuLtpxhmu5gXp55LgYLjHvQE/CI6TMhZbTqfx9A0oH98daeYAsb2dfOv3rRfELeDcxbe40XToy3DpUf66V37EPCL0Q0QmmF1ZW1MdvVBtHC2X++xuUKKK3K12xwmmPyqCoHwsxK3lCM64s3C9uPxMDoe2owTU9ik4AkcTgMM= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853062; x=1707457862; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nvj1miDV4d0e4aC2ZaNqUMG+jiO2D2TtjbXo5NKm+xI=; b=udJ5MTjalup/znrV01+HT2HHuBlifRHAAwQcOvkdb9QPs3pX/W5v/zVmQfae1J18Uc hGUTDcanSfHFsEgXv/XwB52NAMNqHa1qIo58bn0sRx07W4G6wC3UYrfYCPQJDlahQCxE XNLdJ0dIn9rt+4Lx77AfVylGqbDfFsI3tjN/riXEvZOr6VdrrRl62JvD1uXtY/xZj0cM iKARpTvgm8r0gghHnaXWJhB9oeeh5VIl4NUQLGkFEtPBwJ9V4sKkJeEHpUJPlDaDlhVF msolhVhh7GWRfNzXrXmEJstq3UOZvj/VvVNtysRnaXoIuY0las7Pa+d056qfFAx90D+h TVfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853062; x=1707457862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nvj1miDV4d0e4aC2ZaNqUMG+jiO2D2TtjbXo5NKm+xI=; b=afzdqYFJzZ2XnC5yjQC8CD/FNQsXFtQWP7yPR5M2JU23kv9lm03bVds2Qc37PsKDZO M/GsQFK1im5MmGVYtfAqlJHJQawdoujPO2pJTZYMj6kjsSEt0pqR51xNvzNJjibGh27Y 6NV7oEGL5DRWMCetDnPLbaNqGekFE6m7Z54N3LUZkJ2jEVwrpqx4ke4+MyMji1nsYiUM sPerdS6w3FB94ByIhvxt4d7cWpvltRR/z1pClBwymgJWYcRWKD7sqYWIHT02JsXYTw+f Uqp54Mp8jTueE9EZ5Sj3aWDOoAB004mMhZabOp6IuF6jUFj/lIBr1dyH0mMAUxbe4F/s F4Gw== X-Gm-Message-State: AOJu0Yy1AfLBeTAlbuRO+suxhyjWwn0w3jB0Vux3ImrP2G3QZW7nJErK a4FqJycm7eZiaMyd/ajPzPr2cTUcubWb/q6K0GnD5VBWO2nXs8JvlxKdQuXTzf+wrcc2dMMKvMJ kWuY= X-Google-Smtp-Source: AGHT+IFtNLv1eOyVKzCDtTR7jPFM4IA9yXy+AwbWb3RSb89DKVcD3BgQK036qdgX/cKwxAb/NaTTMQ== X-Received: by 2002:a62:cdca:0:b0:6dd:c61e:2026 with SMTP id o193-20020a62cdca000000b006ddc61e2026mr7402503pfg.9.1706853061701; Thu, 01 Feb 2024 21:51:01 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCXRsuNE6gMFdIYwCiZ8pkv8TEZiTHBhzVURFjm7PQHRdv883hJ8FKIjnwq97yrUp2Dvgf7jlPeHnGPq5bfkGSeTEg== From: Richard Henderson To: qemu-devel@nongnu.org Cc: Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 09/57] target/hppa: Populate CPUClass.mmu_index Date: Fri, 2 Feb 2024 15:49:48 +1000 Message-Id: <20240202055036.684176-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853156502100005 Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 7 ++----- target/hppa/cpu.c | 12 ++++++++++++ 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6a153405d2..04439f247d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -281,16 +281,13 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; } =20 +int hppa_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; #else - if (env->psw & (ifetch ? PSW_C : PSW_D)) { - return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); - } - /* mmu disabled */ - return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; + return hppa_cpu_mmu_index(env_cpu(env), ifetch); #endif } =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 3c019855b4..fbb37e541e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -94,6 +94,17 @@ static bool hppa_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 +int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUHPPAState *env =3D cpu_env(cs); + + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); + } + /* mmu disabled */ + return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; +} + static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach =3D bfd_mach_hppa20; @@ -194,6 +205,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; + cc->mmu_index =3D hppa_cpu_mmu_index; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; cc->get_pc =3D hppa_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853392; cv=none; d=zohomail.com; s=zohoarc; b=eZIkBmVJP7fMt7OIvR7VJ2LQhRhQya127Zom2QTvMMAAMuqgHN95iZByPh0MlY8Ehg9G7vLgDwy7YxCxe6Hrfv9aK1Ouok0VChnQpY3+jVcttFXl8GkJzndwhs2HCm1UH44039SDAIqtlJqbzYawfnwMIlwt6DDs1nSKIe1b894= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853392; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qhgRzqqv/s/Iq4v6+M5jYHJ7Q0ZBinPRbaKXKXc9JsM=; b=VkW4jsBmnwWrrZgY5A6Is46TN1RYtRP1truv1oOora3hQXS4OcEoVFLgWQPnTt8peRY8JhcA/6PWkvLTa6fAy7lP/WKdeGHz9Q3Zdq6rqsSUxprEQTztn6zVx7o1ccBfKlGvWpUfNQqKLj8JhtHhSKmyqQSwuX7ZHsNfnlvf+Es= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17068533920169.859255334007685; Thu, 1 Feb 2024 21:56:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSD-0001CW-O3; Fri, 02 Feb 2024 00:51:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSC-0001CO-DN for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:08 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmS9-0001gy-2V for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:06 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6ddc5faeb7fso1441422b3a.3 for ; Thu, 01 Feb 2024 21:51:04 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853063; x=1707457863; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qhgRzqqv/s/Iq4v6+M5jYHJ7Q0ZBinPRbaKXKXc9JsM=; b=Vpv9DpClyoAwEQVHT9X6/F1Pfd7RzfLgWqsnrGs2bIRbbXIcOtVqPwYA19T5h1TxS9 yaGMU6LJNKbzipykA5+rofisntFUsuILVpvPYUtKAPCdnTxsmMIgIqQnew8z0VnZUI+H xpRFoSCAaDm1MMSdzCuBhrrw0cnuerIV3pqFjESoCqIOyd9iiP17/DD4JfmcLzWU6t+F M9vywLtrxnbko6sPf1lW+bxwQiw24mvEDY+4WjLoq3X7zYQJjI1CLxJ0jOIbR0zIcQVn OEJJM6QpU6jsT+eTUiqLsAi71j25S59y6riYOh6BRAosI6XZ7ese5gxUDk5qwNx5q2up ImHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853063; x=1707457863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qhgRzqqv/s/Iq4v6+M5jYHJ7Q0ZBinPRbaKXKXc9JsM=; b=ZDeL1fPvD1uxElFTclek7N0VLt8G2HE/ikacfTE/3tExKWTQB4l8igoN0YEtkKNXnz ZThMX6P4Ic7DPkKzdI5mnZgqFOtadkj2nUt1RIsDyVWtZTWdzqPRcRn5knPOpya9P8Ye FXPW9vwf/ZMzCHrXagC18Dg+y9HtOcT93oSY+xmzcTBt2WlUesg9aXwE7tZNmdPxORwz pPF1AYiYn6cBYu+JvW9ViCRnTF8RwxGQlWZMpb5qk0XOvwO2nKemQfyV5lk2v/cGNaTP nN9yDFIBtoZ7GVZa521kAGKBp0fn2NEpC/a5BpJg79ZUB5EZkzVRMPuDlad1Qbjop/Mb pefg== X-Gm-Message-State: AOJu0YwdTcVWnawxm4B1Pg+0DkjZ3ENJXSpgKdERyqT0VOPd3+G0PY1r 1p05RX6/t5+tx3gwGIfco/RWe1inMcPDm6FLiuEpcz9o7IzwkqVnwuFvTVxpv0KHN7eyFeIKh3e RaoU= X-Google-Smtp-Source: AGHT+IHlLedb+90ytSvxU8vznETy98ZnPOnnihBo9YDTnH9W7A1xbKOCM9ePUcSvbutZDcLcopUKFg== X-Received: by 2002:aa7:86d2:0:b0:6de:3319:ac22 with SMTP id h18-20020aa786d2000000b006de3319ac22mr7553191pfo.2.1706853063710; Thu, 01 Feb 2024 21:51:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 10/57] target/i386: Populate CPUClass.mmu_index Date: Fri, 2 Feb 2024 15:49:49 +1000 Message-Id: <20240202055036.684176-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853393342100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/cpu.h | 13 ++++++------- target/i386/cpu.c | 10 ++++++++++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f0786e8b9..62bdb02378 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2296,13 +2296,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_NESTED_IDX 3 #define MMU_PHYS_IDX 4 =20 -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : - (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; -} - static inline int cpu_mmu_index_kernel(CPUX86State *env) { return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : @@ -2322,6 +2315,12 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) #include "hw/i386/apic.h" #endif =20 +int x86_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) +{ + return x86_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03822d9ba8..280bcb7d00 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7720,6 +7720,15 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } =20 +int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUX86State *env =3D cpu_env(cs); + + return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : + (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) + ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; +} + static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu =3D X86_CPU(cs); @@ -7954,6 +7963,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; + cc->mmu_index =3D x86_cpu_mmu_index; cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; cc->get_pc =3D x86_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853197; cv=none; d=zohomail.com; s=zohoarc; b=WOv2hqvKnsXJWpUn02A6WRcBFFDsZ1h5YkpNqqcNc7TUf+4ZGPjnQjqbAw7bmFFwfmj5h6mtI0ZS+0Zx25y2jNZo47obRUO09WMn3E8GeXHx23o3VUYfZmj6DDSSRd6FyjbyNnAMkXy4mWF+lArBHqdkAqYK5Q1bN2CfawGg5FM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853197; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VAmZNL9zYMPpuAsM9Gmw83HdlClN4X7nwCS0CqUYsPQ=; b=boI40nLONlt2+wlc1q/0FLgrfw4bxVxA25r2jrvxTB6geXn0lZldQivuliS+X1/oo15gEHrRBVGnHrh3nXUesxE178iMcpWgNDtiKvTmLJZ+BgPUWbUBivpD7cQptK0qqtEih+33u/skxEU+IVELBVv0mUJKwGu50e/RSNCHIm8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853197930152.27924458554241; Thu, 1 Feb 2024 21:53:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSF-0001D4-Ji; Fri, 02 Feb 2024 00:51:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSD-0001CX-MZ for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:09 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmSC-0001hk-5r for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:09 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6dfefb490f9so730885b3a.1 for ; Thu, 01 Feb 2024 21:51:06 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853198504100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 6 ++---- target/loongarch/cpu.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 0fa5e0ca93..5dfcfeb3a4 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -408,15 +408,13 @@ struct LoongArchCPUClass { #define MMU_IDX_USER MMU_PLV_USER #define MMU_IDX_DA 4 =20 +int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_IDX_USER; #else - if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { - return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - } - return MMU_IDX_DA; + return loongarch_cpu_mmu_index(env_cpu(env), ifetch); #endif } =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index fb8dde7def..cbecc63213 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -375,6 +375,16 @@ static bool loongarch_cpu_has_work(CPUState *cs) #endif } =20 +int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPULoongArchState *env =3D cpu_env(cs); + + if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + } + return MMU_IDX_DA; +} + static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -779,6 +789,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) =20 cc->class_by_name =3D loongarch_cpu_class_by_name; cc->has_work =3D loongarch_cpu_has_work; + cc->mmu_index =3D loongarch_cpu_mmu_index; cc->dump_state =3D loongarch_cpu_dump_state; cc->set_pc =3D loongarch_cpu_set_pc; cc->get_pc =3D loongarch_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853107; cv=none; d=zohomail.com; s=zohoarc; b=izkL1CWSEexxQC/I/lrwE7didsDiEDujsyhio/EDQi7iz1YTNT2jD5dySub1wVrPJffQTZlHoZRQDsv1A6rQ9wTpVKc5IKGGJxz6obgq8gO9tmAyBgyY44gSlZHQHc2ntU/1b1MDtn8KmoQIUDkhvxhSTuQyoatj5PMM/R0SdWQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853107; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853067; x=1707457867; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RnZ4z27JEwUmWsta9h8D7ESSdJL0MTSBNlDpkb4+YYg=; b=w2b6fwvy2N2HepF4d2jx/bQiNQH4RXRm5SMFpgFrfbbvSlT6VarHBLEBsmFsELt0ks 6xRJ8aUPlPgNjtLTgx4cH14mcAGkD9/2Ji8G4CXx1gAKQw9l/UmwF2q1J55p4n2GIKGv LobTArNHn+kGnm7huoR0gC12KVhijblPrg09FLviKN/NjZOfsv0NDivlq2FunA07Y6FN ltU7HzWWH66su+AT+H8TvO+IbIj89BBqTnI3+AnY6aaMcCWgrmKfN1xj8QqXnkcTNaB9 BquBU2ys7kuz2ifsBuTb31obsxr6KGIAwEzw75ewt1cJD8PzbOFebzBiY7Kyf1NUZyJa OhIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853067; x=1707457867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RnZ4z27JEwUmWsta9h8D7ESSdJL0MTSBNlDpkb4+YYg=; b=uO97eO4IBgJtDT7FbPN7SwmyFF64wFxLKTrlL8hi2MQBa13tcqIoYjIMbgPOFPk3Lp Pq4dzMzjfvbt2dsOKlcJ+0HF1YY38oHgnUV4VJU16V7qQfeoy3ulZdtYAlNNwA/78jiH mdEoDwDd7mQSlrMXPhS9q8A57rHS55ChhvIHaoVMnmKaz67sWzwr6ywHGHHfKjr/HgHm 70XcQpif2q8ocgJyDN7q4GonMZR/M/ONZcT3W4R72+cWwV3drGiNisObNRSqQD6WQtgV ekFAb6QHPjV4mnjpTIZE4KXch+kbEtN3aGhvp1fUhofQqsdk4fzLmsL3/t4ki/EjwGr6 rqDA== X-Gm-Message-State: AOJu0YywlbPWosRZk742zs+5ZMyAsFeWgT4J8MqM+wPft22lKQd73t+U yu3exNSzPn+PcEqOJHmMx5byOYA8VLMEtx75mIwb+wNZHH6a+KXSVUJHSsrVoreVjEgBkQf1GTH +cTA= X-Google-Smtp-Source: AGHT+IGxhQIgc72bx7QdzDED5VEYIXtelv1gx6eKgmlS55EKFPreYPXuBDrZUO9suVobJPDRgxOZAw== X-Received: by 2002:a05:6a00:1491:b0:6dd:892f:e2a6 with SMTP id v17-20020a056a00149100b006dd892fe2a6mr1821005pfu.23.1706853067761; Thu, 01 Feb 2024 21:51:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 12/57] target/loongarch: Rename MMU_IDX_* Date: Fri, 2 Feb 2024 15:49:51 +1000 Message-Id: <20240202055036.684176-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853108381100005 The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. Rename to match generic code. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 8 ++++---- target/loongarch/cpu.c | 2 +- target/loongarch/tcg/tlb_helper.c | 4 ++-- target/loongarch/tcg/translate.c | 2 +- target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 5dfcfeb3a4..47fd110e81 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -404,15 +404,15 @@ struct LoongArchCPUClass { */ #define MMU_PLV_KERNEL 0 #define MMU_PLV_USER 3 -#define MMU_IDX_KERNEL MMU_PLV_KERNEL -#define MMU_IDX_USER MMU_PLV_USER -#define MMU_IDX_DA 4 +#define MMU_KERNEL_IDX MMU_PLV_KERNEL +#define MMU_USER_IDX MMU_PLV_USER +#define MMU_DA_IDX 4 =20 int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY - return MMU_IDX_USER; + return MMU_USER_IDX; #else return loongarch_cpu_mmu_index(env_cpu(env), ifetch); #endif diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index cbecc63213..139acfe373 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -382,7 +382,7 @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); } - return MMU_IDX_DA; + return MMU_DA_IDX; } =20 static void loongarch_la464_initfn(Object *obj) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 449043c68b..65ffbef08e 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -188,8 +188,8 @@ static int get_physical_address(CPULoongArchState *env,= hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type, int mmu_idx) { - int user_mode =3D mmu_idx =3D=3D MMU_IDX_USER; - int kernel_mode =3D mmu_idx =3D=3D MMU_IDX_KERNEL; + int user_mode =3D mmu_idx =3D=3D MMU_USER_IDX; + int kernel_mode =3D mmu_idx =3D=3D MMU_KERNEL_IDX; uint32_t plv, base_c, base_v; int64_t addr_high; uint8_t da =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 235515c629..58674cb268 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -125,7 +125,7 @@ static void loongarch_tr_init_disas_context(DisasContex= tBase *dcbase, if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { ctx->mem_idx =3D ctx->plv; } else { - ctx->mem_idx =3D MMU_IDX_DA; + ctx->mem_idx =3D MMU_DA_IDX; } =20 /* Bound the number of insns to execute to those left on the page. */ diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe= t/loongarch/tcg/insn_trans/trans_privileged.c.inc index 01d457212b..7e4ec93edb 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -323,7 +323,7 @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr= _d) =20 static void check_mmu_idx(DisasContext *ctx) { - if (ctx->mem_idx !=3D MMU_IDX_DA) { + if (ctx->mem_idx !=3D MMU_DA_IDX) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853070; x=1707457870; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mJNaEL6q2/07U1Rp9ME1A8CbXMNqHRbwoUgEMBnXwIs=; b=SrEQ0d9EM9DBbzKXxXh/oLclf0LUmK3iEVBmVEcyWiWYT5Z6HzgKQxTW53SIU3LTBF ocGTPQf2wstPvG80/Jgk2eGvpuRFNkMrCD7kzp3D2VbI0aw9KV54DjU0cVZ5TMUA7wvD c0Rsazvt5DpdSxQ4rZV5D1i/6BC3QZqyqKOoVGecSwjuTAywwtFK0SWsUKcowqS8sjyI FUM5LTbfcXKDKDUkeSTKXJWrYBPY5n1OPPbh+LiHJakXZVXg8y/gS/bMNXKXrIGZdgNa 4o+wF5YcETnIzCH5RIXef3NznO/bmUbDlJoNIIY718zKlIuMBCQlz/LCkm9KEIwm4MTx +V2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853070; x=1707457870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mJNaEL6q2/07U1Rp9ME1A8CbXMNqHRbwoUgEMBnXwIs=; b=bO3JsNHr9FOVPJFqd8Sy23fpqKOJYlYPIGPm4RAJOZRozmhTNWv2tHpAU3+bmJoCdg Q2TBtJl3beEHB26kwv1gSaBdV7R5warHaB0bn9WfFzL4kQtAfZmhdp6bpk06UD7oS/Ge XboZiStO0vhMwNpEMiURI3CrToSH5CiE1HyK4zfZ6zWNoSX1yjMNYBLC1GbYpHfXRtZY sR6fgdsvA0nMfAgNHjCuJBiOYRl8IOzbbRK0jWXnS/NTSPKq1trp0K30dXvOvn8SYkjy lSiYfiKDMsPRCO5WamzAPQhChUBVG0puXn2lIlOnOLAQLAKgcmsRGvx5BJblua7Ux1p9 yzTw== X-Gm-Message-State: AOJu0YzJoTdxJBxVOIu+UjWbjSdfSAnTTrKyluM5AJSZl0kL7GOarVwZ YrVdEouPRFZn3MdFOSgtW1j7IzHUmwMNApGv5szgQgJ8f4QJE9Mwr22CxD6PHAsB+RWa6IA1F0/ sM1M= X-Google-Smtp-Source: AGHT+IH2ERz2cD9E7sMTYnoaRCE2+AER0N8Y3lg4+6BawYjNo8UZTIeCy6ZP+7kBDWSSDZdsrCkRsw== X-Received: by 2002:a05:6808:2089:b0:3be:a295:c54a with SMTP id s9-20020a056808208900b003bea295c54amr8355631oiw.0.1706853069909; Thu, 01 Feb 2024 21:51:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 13/57] target/m68k: Populate CPUClass.mmu_index Date: Fri, 2 Feb 2024 15:49:52 +1000 Message-Id: <20240202055036.684176-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853503671100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/m68k/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 44000f5869..8a8392e694 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -56,6 +56,11 @@ static bool m68k_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 +static int m68k_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return cpu_env(cs)->sr & SR_S ? MMU_KERNEL_IDX : MMU_USER_IDX; +} + static void m68k_set_feature(CPUM68KState *env, int feature) { env->features |=3D BIT_ULL(feature); @@ -551,6 +556,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; + cc->mmu_index =3D m68k_cpu_mmu_index; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; cc->get_pc =3D m68k_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853106; cv=none; d=zohomail.com; s=zohoarc; b=Y43EvY27GWozCajqzHCM3Tb5/m5iSUhxPtNqoXZazKxUmOaDWWdtWnrPId5UcWGXSQ4X2I3Kjl68+9Gf+pEo/kKEp3G3/lKC+xlko9/mncQhY2xsZyk/vjebETpMWyet5olsjCz3935HfFlVrvi47qkiqITXIicGpt5DemQ0iGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853106; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=voMoBx+DmSX4jwUUR+hNTm+Nb2/rGq7GF3Qy4EBDmqw=; b=YmEaCkjKW7JSqyILYpjWm2k42/q9AKeJ/oQ3sHSuFZk3mnuSvESDkIsoJpvDXXJEzrnLd/zNSMiukd2qp+KWc/H6pFB63UCJHyecIfYYp3X9Vc8gBLT0yh90WJiblCm4knCyj5Vr81gJXi0OBzbQimTXFZEFBC16uBB+p92KXJA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853106117883.8855375431382; Thu, 1 Feb 2024 21:51:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSV-0001GR-TF; Fri, 02 Feb 2024 00:51:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSK-0001FM-GL for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:19 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmSH-0001k4-S4 for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:16 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6daf694b439so1369188b3a.1 for ; Thu, 01 Feb 2024 21:51:12 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853106378100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 13 ++----------- target/microblaze/cpu.c | 18 +++++++++++++++++- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5..90ab796de9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -434,19 +434,10 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 +int mb_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) { - MicroBlazeCPU *cpu =3D env_archcpu(env); - - /* Are we in nommu mode?. */ - if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->msr & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; + return mb_cpu_mmu_index(env_cpu(env), ifetch); } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 2318ad7013..6dad11905b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -118,6 +118,22 @@ static bool mb_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 +int mb_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUMBState *env =3D cpu_env(cs); + MicroBlazeCPU *cpu =3D env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->msr & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + #ifndef CONFIG_USER_ONLY static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) { @@ -415,7 +431,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; - + cc->mmu_index =3D mb_cpu_mmu_index; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; cc->get_pc =3D mb_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853421; cv=none; d=zohomail.com; s=zohoarc; b=FklrSJg37YSzFLygKvFH092zddd96SExxFpX3p2A8p8TmXgcBhB/nXt2XICfsiH61rVWG/djmjXYz35so4gZoBA78alZLNvOriWkQxdOOfby3RfxFx1VRZFIvUsDEA6rStcQGHEmg3rTq5FkFudiWaY5ykUZd+mRo/TEYHHjx/4= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853074; x=1707457874; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jy1cBvfDLGAIWcltw0Maq00BzyfiZt9oMrUlfaadwKU=; b=LBjTOy5ikY2/djP5ISxrOBfPFYbCdDw48wh9gMVfk8S7r5jicd/8yuWa56S36RrNwe yo9E7AFLSwF2RytiBbl8bx9mWwuGWqZzR4I8xm3OGHvcqCN1NB8mfPbJAClpyR/WZIu0 /A39aLYJ6U+5YLs6zAop43QFE+ONOZk1iyT5KFhCB7myXRoh6fCm35OY9A5qa22ki/6e GH0ynIjS+reEhmO0/2xH4y/D4COUt5t9zn9Y8hlJaQhPOrG/MjM3Li9cpra0gBdOr8W7 VgsTxKnDyrwyLH62IwYYuiRUGw+JAVQCMFUxotS2sLzilEipIaCozG3wOT1tSo0/2Dmu I6pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853074; x=1707457874; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jy1cBvfDLGAIWcltw0Maq00BzyfiZt9oMrUlfaadwKU=; b=YFAf1XEfOVlU0CQTh2GmJPDNs7V+hRqe8THqTrFRC4jLGh/AY4+wyQAHrHFHzUN5TV SwtPCGM0gpKxKba55Rqm/0V+YGBQBRnXbW3aimmqg/TasZZ0m5saNDcD9HZzNcIIXvEg +XDdFnJFmsKlDKFjrw4+wVAfRqJm2QhyusSAAb74Pggd8NpV1aFrJ/n+YbvQhvxhe5nD RDf6WWwi1I8JlYbl1M4W1E9mRb8l6QLWU/HxHKIpMjmG4YLgu5XoPhBDKxsfqXjSTGRt YbKlF3hkXwljAaQOFZyK6oTjElx//Z7dbg358OrtIL2JG+fQL5ZFAnqVSBoJVXQbLthd Jj8g== X-Gm-Message-State: AOJu0YxB0vrrAJPXZJ9kykDYc40cDdF7VqcYgEcG1iD7xbb4OcqnK8XH ckFItKSRLjLqsgXlJrJs/Vayd/vWHrkNcCj1tT9/IBYozJocmyMyvTRVBD4sKYZflRK7MFflxsu 1jlA= X-Google-Smtp-Source: AGHT+IExzi4Z2GHdQFOxjfytLf0AFnpRMbjhUfPtJW2s8AbVJuAvzrZR4eufimEoD01zx4eck9OgFg== X-Received: by 2002:a05:6a00:1407:b0:6df:f634:4f83 with SMTP id l7-20020a056a00140700b006dff6344f83mr1777323pfu.2.1706853074021; Thu, 01 Feb 2024 21:51:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 15/57] target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill Date: Fri, 2 Feb 2024 15:49:54 +1000 Message-Id: <20240202055036.684176-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853421524100001 Rather than adjust env->hflags so that the value computed by cpu_mmu_index() changes, compute the mmu_idx that we want directly and pass it down. Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/cpu.h | 4 +++- target/mips/tcg/sysemu/tlb_helper.c | 32 ++++++++++++----------------- 2 files changed, 16 insertions(+), 20 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1163a71f3c..3ba8dccd2d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1242,12 +1242,14 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState = *env); * MMU modes definitions. We carefully match the indices with our * hflags layout. */ +#define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 2 +#define MMU_ERL_IDX 3 =20 static inline int hflags_mmu_index(uint32_t hflags) { if (hflags & MIPS_HFLAG_ERL) { - return 3; /* ERL */ + return MMU_ERL_IDX; } else { return hflags & MIPS_HFLAG_KSU; } diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index 4ede904800..b715449114 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -623,7 +623,7 @@ static uint64_t get_tlb_entry_layout(CPUMIPSState *env,= uint64_t entry, static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, int directory_index, bool *huge_page, bool *hgpg_directory_hit, uint64_t *pw_entrylo0, uint64_t *pw_entrylo1, - unsigned directory_shift, unsigned leaf_shift) + unsigned directory_shift, unsigned leaf_shift, int ptw_mmu_idx) { int dph =3D (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; int psn =3D (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; @@ -638,8 +638,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, uint64_t w =3D 0; =20 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { /* wrong base address */ return 0; } @@ -666,8 +665,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, *pw_entrylo0 =3D entry; } if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_= LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return 0; } if (!get_pte(env, vaddr2, leafentry_size, &entry)) { @@ -690,7 +688,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *= vaddr, } =20 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, - int mmu_idx) + int ptw_mmu_idx) { int gdw =3D (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; int udw =3D (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; @@ -776,7 +774,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D goffset; switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -793,7 +791,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D uoffset; switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -810,7 +808,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, vaddr |=3D moffset; switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhi= t, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -825,8 +823,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, /* Leaf Level Page Table - First half of PTE pair */ vaddr |=3D ptoffset0; if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return false; } if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { @@ -838,8 +835,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, v= addr address, /* Leaf Level Page Table - Second half of PTE pair */ vaddr |=3D ptoffset1; if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D - TLBRET_MATCH) { + ptw_mmu_idx) !=3D TLBRET_MATCH) { return false; } if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { @@ -944,12 +940,10 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, * Memory reads during hardware page table walking are performed * as if they were kernel-mode load instructions. */ - int mode =3D (env->hflags & MIPS_HFLAG_KSU); - bool ret_walker; - env->hflags &=3D ~MIPS_HFLAG_KSU; - ret_walker =3D page_table_walk_refill(env, address, mmu_idx); - env->hflags |=3D mode; - if (ret_walker) { + int ptw_mmu_idx =3D (env->hflags & MIPS_HFLAG_ERL ? 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853194546100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/cpu.h | 7 ++++++- target/mips/sysemu/physaddr.c | 2 +- target/mips/tcg/msa_helper.c | 10 +++++----- target/mips/tcg/sysemu/cp0_helper.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 6 files changed, 15 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3ba8dccd2d..4c15e76781 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1255,11 +1255,16 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +static inline int mips_env_mmu_index(CPUMIPSState *env) { return hflags_mmu_index(env->hflags); } =20 +static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +{ + return mips_env_mmu_index(env); +} + #include "exec/cpu-all.h" =20 /* Exceptions */ diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 05990aa5bb..13c8bc8f47 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -236,7 +236,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) int prot; =20 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D 0) { + mips_env_mmu_index(env)) !=3D 0) { return -1; } return phys_addr; diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 7a8dbada5d..d2181763e7 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8214,7 +8214,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_= t df, uint32_t wd, #if !defined(CONFIG_USER_ONLY) #define MEMOP_IDX(DF) \ MemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ - cpu_mmu_index(env, false)); + mips_env_mmu_index(env)); #else #define MEMOP_IDX(DF) #endif @@ -8323,7 +8323,7 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); =20 ensure_writable_pages(env, addr, mmu_idx, ra); @@ -8337,7 +8337,7 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); uint64_t d0, d1; =20 @@ -8358,7 +8358,7 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); uint64_t d0, d1; =20 @@ -8379,7 +8379,7 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); =20 ensure_writable_pages(env, addr, mmu_idx, GETPC()); diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/c= p0_helper.c index cc545aed9c..62f6fb4bf6 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -1202,7 +1202,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulo= ng arg1) old, old & env->CP0_Cause & CP0Ca_IP_mask, val, val & env->CP0_Cause & CP0Ca_IP_mask, env->CP0_Cause); - switch (cpu_mmu_index(env, false)) { + switch (mips_env_mmu_index(env)) { case 3: qemu_log(", ERL\n"); break; diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index 93276f789d..518d3fbc34 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -68,7 +68,7 @@ static void debug_post_eret(CPUMIPSState *env) if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); } - switch (cpu_mmu_index(env, false)) { + switch (mips_env_mmu_index(env)) { case 3: qemu_log(", ERL\n"); break; diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index b715449114..cdae42ffdd 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -973,7 +973,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, ta= rget_ulong address, =20 /* data access */ ret =3D get_physical_address(env, &physical, &prot, address, access_ty= pe, - cpu_mmu_index(env, false)); + mips_env_mmu_index(env)); if (ret =3D=3D TLBRET_MATCH) { return physical; } --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853169; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853170460100004 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index df544ab39b..d644adbc77 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -182,6 +182,11 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } =20 +static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) +{ + return mips_env_mmu_index(cpu_env(cs)); +} + #include "cpu-defs.c.inc" =20 static void mips_cpu_reset_hold(Object *obj) @@ -579,6 +584,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; + cc->mmu_index =3D mips_cpu_mmu_index; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->get_pc =3D mips_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853240; cv=none; d=zohomail.com; s=zohoarc; b=Hk3xkhBzq+b3yGlsslX2b6T6ErOkki8J0RhYUMszVx02rSQScxdcfCzHMr1x6os0qcKAV3gDTcktBq3ziopG3ur56jgOrHEl+Vjg91OHRFMv/5tyypOctt5ilFj87domrErGQ3z93TbyLhjt0qlIQp1L5HuK4vlAN5EBZDJoC7A= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853080; x=1707457880; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NfNpPvlkxn2D3fI9cYf9hBQTlB/c6mteAgGLiKm11to=; b=U+bi+0jsO2Ph593Und3MkaG3KC71v+jFg5gwyHaDbyiom+nTpFaibZkH0qJRuTbSmj Toj0KIp0/x71uzH7iX6xmPwUpag6xIHSl9D70itvKl0jfLsFEbuW/FFNkEWUYIW+gqoH GTxh0wSSvvc4jJBx/kht+srJuG+BlleunkJNSBIpznh/wDkFFPKHSRs5yJOwbQ/J9fIq z/espw1IAm5gyFbOGNqZjJ5qSRei/GI70fdEFXt6qPI+aXUbrr/am9iTxqhrvxnwjHQ8 nJ1YJkVNI5hJ3s0jP2ZghMOqorhNgIWrqex7c1stOxPx8JsRcWtrrbua8VckYU1oAbNS nRkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853080; x=1707457880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NfNpPvlkxn2D3fI9cYf9hBQTlB/c6mteAgGLiKm11to=; b=BoRuJfqM/aWvlikilOAm7mA6p70AeQSdx9cDYAg7mVbqPjBj8eMv6adWAyW3rbG6oJ NxQnCq0jKPwnDY0xQoh0DDP/2raXQ+7uLFikf1grvg7DFVL9wDRw2PQdIY/xcB4YlR9y oEO4TO7G3E3RAlE1eiIsIG4PM3/tWG2ShI/BMzx+9+CPbfLkKMccbJ5dOrF8JnwsNaBw 8k7FufRfr2NuIALzxswIPE4OVvS49SnGg7UYJxL5h9qFFpc3+hx/JunALr5VSdgy3xsb DE7KQvmxxMAnDLT14KG/USUcz3dsIkhvF/s8PdUrg/2hEnIdyWlxC6vwGO3+9mCNbLvh 7U6w== X-Gm-Message-State: AOJu0YwUBnhSa+iBnxH87fPwZLRJVSO3VHmgAKTCHXSp5CZWLcRIVkJR 9PRWT+VWq8D+LEtshv6rPXUzgJrSrmn6djpVgZYwgz80E7zYIUQomC0eY4AlpAGZe/yxt2hPoyw 25Wo= X-Google-Smtp-Source: AGHT+IF1q4Qp7PjjxROAZU8HylUgy+BBcILnA3oAGU/3XeUrUQaW4ivuZmiEZlPxBMM6P3iU921WAQ== X-Received: by 2002:aca:1702:0:b0:3be:ba3c:809a with SMTP id j2-20020aca1702000000b003beba3c809amr7136093oii.34.1706853080222; Thu, 01 Feb 2024 21:51:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 18/57] target/nios2: Populate CPUClass.mmu_index Date: Fri, 2 Feb 2024 15:49:57 +1000 Message-Id: <20240202055036.684176-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853242750100007 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 12 ++++++------ target/nios2/cpu.c | 7 +++++++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2d79b5b298..9965ff74c1 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -270,12 +270,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define MMU_SUPERVISOR_IDX 0 #define MMU_USER_IDX 1 =20 -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : - MMU_SUPERVISOR_IDX; -} - #ifndef CONFIG_USER_ONLY hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -292,6 +286,12 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 =3D=3D 0. */ =20 +int nios2_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) +{ + return nios2_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 596c0c5617..e42885997e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -57,6 +57,12 @@ static bool nios2_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 +int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return (cpu_env(cs)->ctrl[CR_STATUS] & CR_STATUS_U + ? MMU_USER_IDX : MMU_SUPERVISOR_IDX); +} + static void nios2_cpu_reset_hold(Object *obj) { CPUState *cs =3D CPU(obj); @@ -381,6 +387,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; + cc->mmu_index =3D nios2_cpu_mmu_index; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->get_pc =3D nios2_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853229; cv=none; d=zohomail.com; s=zohoarc; b=EXXKj5cUz9WCw4r1vAg7EBtEVnnwcRcKOqWcFuDOZGHr1YyGOBI5bwVtcq4UcudgPKgWun/Lfn8Mv4HrTVrSL+LTYUWMFi2VSeMW4r7o48Yf6Oylflf1Rfc2cLRz4YyxXHmfblkkMGHQ3DTxoIagPuOnulAs44nhBFGhUuZHtNA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853229; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2tz+hZT+/jj7B5V0fs8mig9BK9nxx7zGxdWkFBgn124=; b=RHtMyfZDeMml/0mKYYGr6pCvX8HwlJNtghmyW0XKEjInkBddj4AaSJumAe1E/ivTiCBTllw+mvIgNXGBRj4I6yJBT/kjMNzn5AYq/HZquOlRRAtZzT5nXa30m0vPpAFLpzZirl2DSQUOePtOcaWP7fDxsscI0RjgfNBvWZIHPWo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853229044105.0115023866598; Thu, 1 Feb 2024 21:53:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSZ-0001Hl-NE; Fri, 02 Feb 2024 00:51:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmST-0001GN-FX for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:25 -0500 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmSS-0001os-1m for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:25 -0500 Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3beb504c985so909887b6e.0 for ; Thu, 01 Feb 2024 21:51:23 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853082; x=1707457882; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2tz+hZT+/jj7B5V0fs8mig9BK9nxx7zGxdWkFBgn124=; b=WdJEf4dzq4RaTvYC6zJkQgSq89K5j2/aGr2hWPPnsPkjhTOivr+m1R+LI0j7VMai73 HpuHU9r1t2E6oa1fl+ZKyjOLAGiBdOBZYo0gtQ9H4VanpksyYP+Wy87X0J7rIzor7M6Z OxeUiX/aUbgjYz2gqwYRIEHLyEBVliuPw6+5c6AZDENAFRySsxOy8mBrZXso5+tXMXGy o+x6RsxFgFYH+stoAqY6lRNS2nRhsBuZDOT9qNOft+5vE/UN6lSLzMmX4Tm1JQkihYi2 9LrM9MCaU+piwXuZb2i+a/X1Z6XXCdQx2fx+KM2TNibjbZuMgd3yttsbVr2o0HXl6WyR b0SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853082; x=1707457882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2tz+hZT+/jj7B5V0fs8mig9BK9nxx7zGxdWkFBgn124=; b=KKd2UMvgRDj241GgQJ4+213J/y+33jzeMe0ImFD7UJ2u7W1T/jhu1uItWRTdVN62tl nppDZ1lGhFM3Bskla9k8f3jc38j86JainxrWrQO9rYIaJ+aBz/gGX3UVpCk4LLnj9/WM g7PKxRHMaMJxjB+RGPSXnS7Zr6AvnjOdpxSB3ibzrwl99XxkIQCKPA/3nnn0uY9RtCJe w0TBi97/yYEdftUsytcslahi0N1eLlt1QAoVxrYmE4Fl+UeLtelBSE7Yvta6Cu8Zp1ar 7K++mlYjB4k7EQ7PWAqEEbj38DW8xeAL+G524v2aP3+tJfkfeQcfJA0Xp4f5Ni/Eyzec WTNA== X-Gm-Message-State: AOJu0YyUdFBUq+AOEmx3sur2dwasbyYRA/LkmIvcBuE0muBExSAUswGs 5EhOZcyzhylehDBgUIS62fWOZnhM7u0vO2jk6t95HhYg8nexLlPFS4JhlriaoOOz+8ZuXh7Jbv+ TjH4= X-Google-Smtp-Source: AGHT+IFn5LB9C5Z8+1h902WWekza8vND9DBwFzX6tGKRPAe1+zHdIAv5qyp3+iLsyxGHJhJUhVM/4g== X-Received: by 2002:a05:6808:2098:b0:3be:c43a:97c7 with SMTP id s24-20020a056808209800b003bec43a97c7mr7787786oiw.24.1706853082234; Thu, 01 Feb 2024 21:51:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 19/57] target/openrisc: Populate CPUClass.mmu_index Date: Fri, 2 Feb 2024 15:49:58 +1000 Message-Id: <20240202055036.684176-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853230732100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 10 ++-------- target/openrisc/cpu.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b454014ddd..7dbed8d8be 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,16 +361,10 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCSt= ate *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } =20 +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { - int ret =3D MMU_NOMMU_IDX; /* mmu is disabled */ - - if (env->sr & (ifetch ? SR_IME : SR_DME)) { - /* The mmu is enabled; test supervisor state. */ - ret =3D env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; - } - - return ret; + return openrisc_cpu_mmu_index(env_cpu(env), ifetch); } =20 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 477d49d4bc..8670152c84 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -68,6 +68,18 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } =20 +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUOpenRISCState *env =3D cpu_env(cs); + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; + } + + return MMU_NOMMU_IDX; /* mmu is disabled */ +} + static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { info->print_insn =3D print_insn_or1k; @@ -239,6 +251,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; + cc->mmu_index =3D openrisc_cpu_mmu_index; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->get_pc =3D openrisc_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853395; cv=none; d=zohomail.com; s=zohoarc; b=WtpMIyOEpIKp16vHl2lXPSDcYeHa2sbcjXPuFulcFhZo28M5UMTPqUTJI5uWbBThi0Xwo/4kFP0OGEeNt60Sdw4HgaQxeQwsRrx2tVI2ljJ717McK5tWAD8P3BqQzsPMUyJoF9mFYg0lKKRKMIVYgVHhAjDS9dSq5U9KkxUW/Hk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853395; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HgdbWgNLg8LLScF7lhaba0ocAypckeHfyh0foJfM/Y8=; b=ejptloyswz3pbDLsYgn+REX10JPbKocdUa/PUrI6Pym1CLZpr7vd8GR5jj301sSkD3wbFiZUZaxJ5QRNA17od0lyJfxHp8ZHGBZFn1WTYCAmn29mcjZJVKR4u7+oQzgH0jiRUA5qqsGC3Jxkyf9kiVi+bJ71DNn37geAEP5k6UE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853395914403.4981420526635; Thu, 1 Feb 2024 21:56:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSe-0001Mg-3k; Fri, 02 Feb 2024 00:51:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSV-0001H8-JY for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:27 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmST-0001py-Ti for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:27 -0500 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-5ca29c131ebso1526164a12.0 for ; Thu, 01 Feb 2024 21:51:25 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853397444100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 7 ++++++- target/ppc/cpu_init.c | 2 +- target/ppc/mem_helper.c | 10 +++++----- target/ppc/mmu_common.c | 4 ++-- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..5f4f52aec5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1624,7 +1624,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint3= 2_t val); =20 /* MMU modes definitions */ #define MMU_USER_IDX 0 -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) +static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; @@ -1633,6 +1633,11 @@ static inline int cpu_mmu_index(CPUPPCState *env, bo= ol ifetch) #endif } =20 +static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) +{ + return ppc_env_mmu_index(env, ifetch); +} + /* Compatibility modes */ #if defined(TARGET_PPC64) bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23eb5522b6..86c8031765 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7457,7 +7457,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " "%08x iidx %d didx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, - cpu_mmu_index(env, true), cpu_mmu_index(env, false)); + ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, fals= e)); #if !defined(CONFIG_USER_ONLY) if (env->tb_env) { qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index c7535481d6..ea7e8443a8 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -83,7 +83,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ul= ong addr, uint32_t nb, void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D ppc_env_mmu_index(env, false); void *host =3D probe_contiguous(env, addr, (32 - reg) * 4, MMU_DATA_LOAD, mmu_idx, raddr); =20 @@ -105,7 +105,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, ui= nt32_t reg) void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D ppc_env_mmu_index(env, false); void *host =3D probe_contiguous(env, addr, (32 - reg) * 4, MMU_DATA_STORE, mmu_idx, raddr); =20 @@ -135,7 +135,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr,= uint32_t nb, return; } =20 - mmu_idx =3D cpu_mmu_index(env, false); + mmu_idx =3D ppc_env_mmu_index(env, false); host =3D probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr= ); =20 if (likely(host)) { @@ -224,7 +224,7 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, u= int32_t nb, return; } =20 - mmu_idx =3D cpu_mmu_index(env, false); + mmu_idx =3D ppc_env_mmu_index(env, false); host =3D probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, radd= r); =20 if (likely(host)) { @@ -276,7 +276,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong = addr, target_ulong mask, dcbz_size =3D env->dcache_line_size; uint32_t i; void *haddr; - int mmu_idx =3D epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); + int mmu_idx =3D epid ? PPC_TLB_EPID_STORE : ppc_env_mmu_index(env, fal= se); =20 #if defined(TARGET_PPC64) /* Check for dcbz vs dcbzl on 970 */ diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 6ca5d12207..751403f1c8 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1561,9 +1561,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) * mapped by code TLBs, so we also try a MMU_INST_FETCH. */ if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, - cpu_mmu_index(&cpu->env, false), false) || + ppc_env_mmu_index(&cpu->env, false), false) || ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, - cpu_mmu_index(&cpu->env, true), false)) { + ppc_env_mmu_index(&cpu->env, true), false)) { return raddr & TARGET_PAGE_MASK; } return -1; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853180; cv=none; d=zohomail.com; s=zohoarc; b=mEPqohelbKEfBvu4QnqtlrhA2iMYYqniE7wbvx1sPH1oaT4TGUbnjYBWcOJH+5fQVp0H/7sSG42a+aRN/kCbeBPpgfXNvxj9NtdWmKdQO0wxxRH3XeQZQdpu7fpZGfPrYV7Y3kYcAADQUirgp5J41o1fxbcEF9IA47UcYm68Ra0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853180; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m31ykn6MQscxmLhUVwK1jeDu4gpHyJfjJcp6vG3u6hA=; b=dqAbxByZ6a1ezSZbLuZgypj/uNn2aBNkRbRSuiPLKRv0nT8y3IfNIBactdnNIFcTb9DIOsbYkIUqMyKuclRTyExe6wpLQMU9SVLzlQfEpucSe1RHEHSCzVjWSvZslpNx91wUl5d/6sIA75QdYtUU957OLSsEq+dYr1Bx7Gg6xiA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853180886345.1667380155967; Thu, 1 Feb 2024 21:53:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSh-0001PU-Gh; Fri, 02 Feb 2024 00:51:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSX-0001Hg-Lk for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:29 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmSV-0001qg-Vm for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:29 -0500 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6ddd19552e6so1100649b3a.1 for ; Thu, 01 Feb 2024 21:51:27 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853182512100005 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/ppc/cpu_init.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 86c8031765..9931372a08 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7105,6 +7105,11 @@ static bool ppc_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 +static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return ppc_env_mmu_index(cpu_env(cs), ifetch); +} + static void ppc_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); @@ -7372,6 +7377,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D ppc_cpu_class_by_name; cc->has_work =3D ppc_cpu_has_work; + cc->mmu_index =3D ppc_cpu_mmu_index; cc->dump_state =3D ppc_cpu_dump_state; cc->set_pc =3D ppc_cpu_set_pc; cc->get_pc =3D ppc_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853187; cv=none; d=zohomail.com; s=zohoarc; b=IEicK5QU/lhNW9nq52M7G0N7RyWZEzaLQgP32EfuTtbnDYuYGYCD5ZH6cdx11OxWgUxwbkp4jKQo7J1woh9Npb6qd3TqsotK4EhEwXtL79L66smTW0gpyGyebRpWrDYbzlHpYc/IwxbwmXjTvbLt28RX5dbEKzzDCScVa+LKcN8= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853089; x=1707457889; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sWFZsOSqQ4Z7s/RrBOUjbekx6H9vQkuMkzZGGFe3Im0=; b=W7YdEQnVTZm1E+XRNk242GMHeNWOH1qFod6Kmi88nZ/KBAE9M2q7eLcFqNdgMT3gR2 opKvTg5ZO51oVx+/rugUpNpvWpmNae5kVC21Ypto5+qvjQLHmnGUszEHyQlSPjcPTijh yFM4heYRMVWhED/DQf7rDrBR6CzRx4eYslbzanEPOZzyWzBDg1Znk1/RY1a+G7Qc7/rq uiIIi5i/ARuiO41z+e3C6Pnm2AqSGm31Xv0COECmCSX/cUNquAK4YDuBduz737vS+WeH cCObHpZzjxfR8BB0rPx8Ct3vxfCDUo3hUydbHafzfr/4eCvA6Yz0sFm8GCkqkIUrh0Hc tYdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853089; x=1707457889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sWFZsOSqQ4Z7s/RrBOUjbekx6H9vQkuMkzZGGFe3Im0=; b=Rr3ZPWzv9ckVgivMwNbBdAW6LFyM2RPigieXNBcEHkdjD3ir5u+cnw+x539vkgOVek xtKpxrnAqGGUX8yCysI4tbsS5pgc2K6Yqq7iuQWq/3BvwVsEhVkJIMv2KmhxusRzSjDv CfrB+e7dwW3r6A1FCsP4tB8X4X+yxM8+TE/dBKb8swO/A+2e1/zKM1XEXKBturzbSFGl ii8900aql8OGeZSQnLi7GUbLYNf3KkVj3sa7Qy711uSe5DQeXw5t34QK45AQ/Q3ZZEqp DlMbBKxkrZQaiEXYRzCxRJUitYg6yi4i6pKPDhAps3bT4Kk1S1SbEAfXconUYsNXoMf0 LcoA== X-Gm-Message-State: AOJu0YxLm85ln99k9Qk9LVkZUgRm6cEfDKVkD8YCUFNOh+w32k/3dw74 XGpq9T3/qlF4QTsXtQHnKEAutSD445mMJW3X8IiCQVRQH+XBkGHqJCTFXemiWYLTkl1OPtG/fl2 MbZ0= X-Google-Smtp-Source: AGHT+IFJwoe2kooifa0wLSBMTpsA4TVctULJ+1tUkgok+1PYGkj+jLrCrulGK+uimCKSZYvRCrVGkA== X-Received: by 2002:a05:6808:1509:b0:3be:1e78:22ed with SMTP id u9-20020a056808150900b003be1e7822edmr5632468oiw.21.1706853089099; Thu, 01 Feb 2024 21:51:29 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCUu6JinBY+v8G7V6njozTEJik9Y4q+ycaEF6l+46X2yJyexpTENwS1AIDncXHxt2jm4c2NENh2wZSVKNu9ssYklSA== From: Richard Henderson To: qemu-devel@nongnu.org Cc: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 22/57] target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index Date: Fri, 2 Feb 2024 15:50:01 +1000 Message-Id: <20240202055036.684176-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853188527100001 Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu_helper.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f3955c38d..9c825c7b51 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,7 +498,7 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); @@ -507,7 +507,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); =20 -#define cpu_mmu_index riscv_cpu_mmu_index +#define cpu_mmu_index riscv_env_mmu_index =20 #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..15f87ecdb0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -33,7 +33,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" =20 -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853344; cv=none; d=zohomail.com; s=zohoarc; b=Eh7+dZ4oi0m/UWTLqpubp7nsRG5V1ZqlopD19pOodWGxAtU5/l8IHiDCnJuqKGfsrgjtONlDKz1xn67/J4Gaemt3lk1I1DItZ+5YGIDgtszDwTYUYfxv2MTT3H54dxAlIrBeUuvjeXUGBlZNUP0mErwvpdpy7fT9h+DfUfX2490= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853344; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ms7csWcwYHLSl8fSIIPTDjdA8uF4eqoYfqQ702PkMLU=; b=V9jqSXrnraKl2+L3+K+VzUN/NQPPRBzsY5bJZ7PzXEACVU6v3ouA00fLSPp4dMwvCac218BmZbdpzJKVrgeUuW+iaNjlZc584aHG9VtVZUC2Wevlfa1fGbR+C/V4ujSTBlFxjbiCW4M4zTR1HfwjzPJbSVzmFziprq0iMam5/Lg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853344115452.7029830601664; Thu, 1 Feb 2024 21:55:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSj-0001Se-NQ; Fri, 02 Feb 2024 00:51:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSc-0001Lu-P2 for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:35 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmSb-0001sj-1h for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:34 -0500 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-5d8b519e438so1686104a12.1 for ; Thu, 01 Feb 2024 21:51:32 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853091; x=1707457891; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ms7csWcwYHLSl8fSIIPTDjdA8uF4eqoYfqQ702PkMLU=; b=MY9jpEdjrQ0Am71VNtrd8jvXoRgoZhLeixpq3TkfRwQuTgj57I2AJhwg+elZPSrYeJ y8w/SzXi++aAvtkIz6iQP6br59hy3XsS9a4hp5r2cZL1n0jKr0xKJFau4i+jercUSCeL 8oa3yPFTJ/XgH/pX4ET2WMTQEqYAx7PugF+ighEtAaceiFkibJM33Bq8JViN7n5WUnCn 56p2ETWKAu130Jx/VQ7s0smjnv+xm/Zt/I4Ljh8QZKOU++KbDf2ICBb5lRMvOtvEV1lC G1HiEyBfa9vZamHaF8hoeXaX6b6O4RaLYrZluoK9Ir8RPqRuf9ZEyYqp7qxJHoXCDv85 FBVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853091; x=1707457891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ms7csWcwYHLSl8fSIIPTDjdA8uF4eqoYfqQ702PkMLU=; b=BPcm41lA23tCnsaLgRDzSQxTImAhzrpEBSmkst8dOsdYORHSxE3C6N1xhPVD8bYDNV Nr0LmRs0TKL+p98K10iQvhOqgi0mzZY8QPNO9i24aKSKdixLu9bzx0RBblhu4fXjURNS mbzcWasFGz4XyMyrCt7hd4i6kgYnZwzgPkmg9dWnxvRUF73K9El21E+jiKiKKntA6gcD Y3SMFOMbFfHnagnA2gQsDVwhkrpMhY3tO7eSp7JIW1+q7L7kAJWHmT+T01JGivoihyZ1 s6nod8Yk6tXlyYlssg3RngSkVI2pe2spdTkWw6VuvtFV8MRzzyuSnDTNL3lPu2qpL4eL VQqw== X-Gm-Message-State: AOJu0YxmZ2opVzGX+7eVMNl30xtd6T2HECVy4bprTqaWsyBN2b6AwDss dyyVnPZlQtIEdMA6n33UUOXfEOpSlX6r2MoC5OR+9sSidSQWt0cDp2q0c9UU8LgHlQ01PEjI4LD bIZQ= X-Google-Smtp-Source: AGHT+IEND4wlQpwpse0QwcTqyRAAjrKfm+TsZ39TAUK/IwvOF63Ckc6jYzmsrbh77srb6GbDGgQvHw== X-Received: by 2002:a05:6a20:d393:b0:19c:a7e5:37cc with SMTP id iq19-20020a056a20d39300b0019ca7e537ccmr5948283pzb.41.1706853091440; Thu, 01 Feb 2024 21:51:31 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCV+iEpVpPMnk0B3LZSjT3zrp3LIUjiS7tlhzWvWcBXEg5Lr6pM2n/bWuqqGNFte92wYD/D4bOMrU/uneQHrXT2Hpg== From: Richard Henderson To: qemu-devel@nongnu.org Cc: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 23/57] target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index Date: Fri, 2 Feb 2024 15:50:02 +1000 Message-Id: <20240202055036.684176-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853345286100001 Use the target-specific function name in preference to the generic name. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 4 ++-- target/riscv/op_helper.c | 4 ++-- target/riscv/vector_helper.c | 9 +++++---- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 15f87ecdb0..b6b23b7d03 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -106,7 +106,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, #else flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); =20 - flags |=3D cpu_mmu_index(env, 0); + flags |=3D riscv_env_mmu_index(env, 0); fs =3D get_field(env->mstatus, MSTATUS_FS); vs =3D get_field(env->mstatus, MSTATUS_VS); =20 @@ -1200,7 +1200,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) CPURISCVState *env =3D &cpu->env; hwaddr phys_addr; int prot; - int mmu_idx =3D cpu_mmu_index(&cpu->env, false); + int mmu_idx =3D riscv_env_mmu_index(&cpu->env, false); =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, true, env->virt_enabled, true)) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5355225d56..f414aaebdb 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -157,7 +157,7 @@ void helper_cbo_zero(CPURISCVState *env, target_ulong a= ddress) { RISCVCPU *cpu =3D env_archcpu(env); uint16_t cbozlen =3D cpu->cfg.cboz_blocksize; - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D riscv_env_mmu_index(env, false); uintptr_t ra =3D GETPC(); void *mem; =20 @@ -205,7 +205,7 @@ static void check_zicbom_access(CPURISCVState *env, uintptr_t ra) { RISCVCPU *cpu =3D env_archcpu(env); - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D riscv_env_mmu_index(env, false); uint16_t cbomlen =3D cpu->cfg.cbom_blocksize; void *phost; int ret; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c1c3a4d1ea..fe0d5d053c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -113,14 +113,15 @@ static void probe_pages(CPURISCVState *env, target_ul= ong addr, { target_ulong pagelen =3D -(addr | TARGET_PAGE_MASK); target_ulong curlen =3D MIN(pagelen, len); + int mmu_index =3D riscv_env_mmu_index(env, false); =20 probe_access(env, adjust_addr(env, addr), curlen, access_type, - cpu_mmu_index(env, false), ra); + mmu_index, ra); if (len > curlen) { addr +=3D curlen; curlen =3D len - curlen; probe_access(env, adjust_addr(env, addr), curlen, access_type, - cpu_mmu_index(env, false), ra); + mmu_index, ra); } } =20 @@ -464,6 +465,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t esz =3D 1 << log2_esz; uint32_t vma =3D vext_vma(desc); target_ulong addr, offset, remain; + int mmu_index =3D riscv_env_mmu_index(env, false); =20 /* probe every access */ for (i =3D env->vstart; i < env->vl; i++) { @@ -478,8 +480,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, remain =3D nf << log2_esz; while (remain > 0) { offset =3D -(addr | TARGET_PAGE_MASK); - host =3D tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)); + host =3D tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_i= ndex); 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+} + static void riscv_cpu_reset_hold(Object *obj) { #ifndef CONFIG_USER_ONLY @@ -1810,6 +1815,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; + cc->mmu_index =3D riscv_cpu_mmu_index; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; cc->get_pc =3D riscv_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853366; cv=none; d=zohomail.com; s=zohoarc; b=Koqt+sSHBcB+dxcI8jqq6mJovOkgih8CO7baepeqKKVdCq57P46CRCUYaKAkSJm7RoQ+ahD6szVDfqL6nYAtcTswowUzXFyFfixL7k38sl1hEd/S9oMpzdEGa2ahYICvA/thPmoR3j+Uvgf1nLes9jFwI3qQ7ZwXntbTNKRrLaE= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853367299100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/rx/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 353132dac2..5205167da1 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -64,6 +64,11 @@ static bool rx_cpu_has_work(CPUState *cs) (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } =20 +static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc) +{ + return 0; +} + static void rx_cpu_reset_hold(Object *obj) { RXCPU *cpu =3D RX_CPU(obj); @@ -204,6 +209,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) =20 cc->class_by_name =3D rx_cpu_class_by_name; cc->has_work =3D rx_cpu_has_work; + cc->mmu_index =3D riscv_cpu_mmu_index; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; cc->get_pc =3D rx_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853250; cv=none; d=zohomail.com; s=zohoarc; b=Jx8jzZfyNNhK1IfOnc9c7dAnf2a0ia2Gh7h97i/uQJBec+vTEgyODIordhNmMkO8TkyylmOOoZvgjxT+ehekX3c6iFihF/wizRDOTSJssb7ujVvQZElMqlCMNLtHDZhVI6eoKvwFEIYNYOvS3M1s7elklMIJfjtVagWDluMs1MY= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853250775100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 4 +++- target/s390x/tcg/mem_helper.c | 34 ++++++++++++++++++---------------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f97..f0fed5d6ad 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -381,7 +381,7 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 =20 -static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) +static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; @@ -412,6 +412,8 @@ static inline int cpu_mmu_index(CPUS390XState *env, boo= l ifetch) #endif } =20 +#define cpu_mmu_index s390x_env_mmu_index + #ifdef CONFIG_TCG =20 #include "tcg/tcg_s390x.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 84103251b9..557831def4 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -358,7 +358,7 @@ static int mmu_idx_from_as(uint8_t as) static uint32_t do_helper_nc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c =3D 0; @@ -392,7 +392,7 @@ uint32_t HELPER(nc)(CPUS390XState *env, uint32_t l, uin= t64_t dest, static uint32_t do_helper_xc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c =3D 0; @@ -433,7 +433,7 @@ uint32_t HELPER(xc)(CPUS390XState *env, uint32_t l, uin= t64_t dest, static uint32_t do_helper_oc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c =3D 0; @@ -467,7 +467,7 @@ uint32_t HELPER(oc)(CPUS390XState *env, uint32_t l, uin= t64_t dest, static uint32_t do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t des= t, uint64_t src, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca, desta; uint32_t i; =20 @@ -508,7 +508,7 @@ void HELPER(mvc)(CPUS390XState *env, uint32_t l, uint64= _t dest, uint64_t src) /* move right to left */ void HELPER(mvcrl)(CPUS390XState *env, uint64_t l, uint64_t dest, uint64_t= src) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); const uint64_t ra =3D GETPC(); S390Access srca, desta; int32_t i; @@ -529,7 +529,7 @@ void HELPER(mvcrl)(CPUS390XState *env, uint64_t l, uint= 64_t dest, uint64_t src) /* move inverse */ void HELPER(mvcin)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t= src) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca, desta; uintptr_t ra =3D GETPC(); int i; @@ -550,7 +550,7 @@ void HELPER(mvcin)(CPUS390XState *env, uint32_t l, uint= 64_t dest, uint64_t src) /* move numerics */ void HELPER(mvn)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t s= rc) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uintptr_t ra =3D GETPC(); int i; @@ -572,7 +572,7 @@ void HELPER(mvn)(CPUS390XState *env, uint32_t l, uint64= _t dest, uint64_t src) /* move with offset */ void HELPER(mvo)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t s= rc) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); /* MVO always processes one more byte than specified - maximum is 16 */ const int len_dest =3D (l >> 4) + 1; const int len_src =3D (l & 0xf) + 1; @@ -606,7 +606,7 @@ void HELPER(mvo)(CPUS390XState *env, uint32_t l, uint64= _t dest, uint64_t src) /* move zones */ void HELPER(mvz)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t s= rc) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uintptr_t ra =3D GETPC(); int i; @@ -669,7 +669,7 @@ uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, u= int32_t mask, =20 if (!mask) { /* Recognize access exceptions for the first byte */ - probe_read(env, addr, 1, cpu_mmu_index(env, false), ra); + probe_read(env, addr, 1, s390x_env_mmu_index(env, false), ra); } =20 while (mask) { @@ -893,7 +893,7 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, = uint32_t r1, uint32_t r2) { const uint64_t src =3D get_address(env, r2) & TARGET_PAGE_MASK; const uint64_t dst =3D get_address(env, r1) & TARGET_PAGE_MASK; - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); const bool f =3D extract64(r0, 11, 1); const bool s =3D extract64(r0, 10, 1); const bool cco =3D extract64(r0, 8, 1); @@ -946,7 +946,7 @@ inject_exc: /* string copy */ uint32_t HELPER(mvst)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); const uint64_t d =3D get_address(env, r1); const uint64_t s =3D get_address(env, r2); const uint8_t c =3D env->regs[0]; @@ -1027,7 +1027,7 @@ static inline uint32_t do_mvcl(CPUS390XState *env, uint64_t *src, uint64_t *srclen, uint16_t pad, int wordsize, uintptr_t ra) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); int len =3D MIN(*destlen, -(*dest | TARGET_PAGE_MASK)); S390Access srca, desta; int i, cc; @@ -1084,7 +1084,7 @@ static inline uint32_t do_mvcl(CPUS390XState *env, /* move long */ uint32_t HELPER(mvcl)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const int mmu_idx =3D s390x_env_mmu_index(env, false); uintptr_t ra =3D GETPC(); uint64_t destlen =3D env->regs[r1 + 1] & 0xffffff; uint64_t dest =3D get_address(env, r1); @@ -1742,7 +1742,7 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1= , uint32_t r2, static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { - uint32_t mem_idx =3D cpu_mmu_index(env, false); + uint32_t mem_idx =3D s390x_env_mmu_index(env, false); MemOpIdx oi16 =3D make_memop_idx(MO_TE | MO_128, mem_idx); MemOpIdx oi8 =3D make_memop_idx(MO_TE | MO_64, mem_idx); MemOpIdx oi4 =3D make_memop_idx(MO_TE | MO_32, mem_idx); @@ -2867,12 +2867,14 @@ uint32_t HELPER(cu42)(CPUS390XState *env, uint32_t = r1, uint32_t r2, uint32_t m3) void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len, uintptr_t ra) { + const int mmu_idx =3D s390x_env_mmu_index(env, false); + /* test the actual access, not just any access to the page due to LAP = */ while (len) { const uint64_t pagelen =3D -(addr | TARGET_PAGE_MASK); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853507689100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7f123863dc..49a2341acc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -142,6 +142,11 @@ static bool s390_cpu_has_work(CPUState *cs) return s390_cpu_has_int(cpu); } =20 +static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return s390x_env_mmu_index(cpu_env(cs), ifetch); +} + static void s390_query_cpu_fast(CPUState *cpu, CpuInfoFast *value) { S390CPU *s390_cpu =3D S390_CPU(cpu); @@ -352,6 +357,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) scc->reset =3D s390_cpu_reset; cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; + cc->mmu_index =3D s390x_cpu_mmu_index; cc->dump_state =3D s390_cpu_dump_state; cc->query_cpu_fast =3D s390_query_cpu_fast; cc->set_pc =3D s390_cpu_set_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853344; cv=none; d=zohomail.com; s=zohoarc; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853102; x=1707457902; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oklbVSJHBuHU9hGmj0c6860U12/l0p2//g5ungqfTvk=; b=otiZEslkfmF/83oDlvRF6XIFN1bIY42qpi/0gxWUOs+zYul9hu13EVASxG2U6xBn3A pCWZwHd+BaFALtwOmDHp3iQMKJwyh74Pu7cQ3isEJxM48Mch4e4oIy23poGtTv7dacC/ c106LaQ7DGhm6qDPxFFD9+t3o0J5UauAkIUMqc5sX0yWKkV5bCO+EUrEsk7+EgtsjwwU CEQqjnIkKAf1bTSKIbsbxwkiBh589uknbQz1PjfJse4j3Q9x+mBLuvdelZxeiZKhbPuk 25iQ6XNvTyAvO3B+OCYotJttNtf029yjSXWIFN9Q1Sgnny68g3N5rNYKa0YmZf3TNmwd i9mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853102; x=1707457902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oklbVSJHBuHU9hGmj0c6860U12/l0p2//g5ungqfTvk=; b=Y0uI/RqYHJcy4FaVBlzqaGSDEkcekYAm2dvQLgTpooQQcv28qBjlo9enNChZz8QlQ9 7kIS74hDseLeVG4Bb7Ul+6DC46kx4HLvxvJsfVxOijwiBtLGsUMc1GmdeMh/2N+EQ3q8 95Lml0jYyGOPbEg3dQP63kXK5ul59DHkmW2j1x38407WeXF5a/tbMXfJu4Tv+qBgxDEM 191TMJ9xdiby5iJ5cWBHCc1sKZVflgKy1oZRtBHBbSKmc2IauO/SR9kIcLq+jpmuIiyz +uoBezjaCaWZbJJEkcYeqRqz3CbdGU2UBR/YAaM5ZCR55bNU1Z8uiN58YSVwiLkNcFjf 3gpQ== X-Gm-Message-State: AOJu0YxM/pGsrl2zvWnQ2/lq5SWayXPJzSSeqgg/f0y947x48GX01KwF si4ahGWcppQJFTkyyCAAVSjouoeIdHu75t7nEpqGmb19Hnb1mJZWfsm9Iu5Zp86c/jbqiJfb8Z4 xpPU= X-Google-Smtp-Source: AGHT+IH9G8eTVAi4dV+r/7JaqNaQr3qT8glARJtiYQV32X1GOHs3RZkuJwlOD4qVJlQVLI1L/r4XhQ== X-Received: by 2002:a05:6a00:9291:b0:6d9:955a:d3bb with SMTP id jw17-20020a056a00929100b006d9955ad3bbmr2047067pfb.10.1706853101893; Thu, 01 Feb 2024 21:51:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 28/57] target/sh4: Populate CPUClass.mmu_index Date: Fri, 2 Feb 2024 15:50:07 +1000 Message-Id: <20240202055036.684176-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853345297100002 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 16 ++++++---------- target/sh4/cpu.c | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 0e6fa65bae..9c5e2b349e 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -273,16 +273,6 @@ void cpu_load_tlb(CPUSH4State * env); =20 /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) -{ - /* The instruction in a RTE delay slot is fetched in privileged - mode, but executed in user mode. */ - if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { - return 0; - } else { - return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; - } -} =20 #include "exec/cpu-all.h" =20 @@ -380,6 +370,12 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 +int sh4_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUSH4State *env, bool ifetch) +{ + return sh4_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 39772955b5..6fead5655f 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -89,6 +89,21 @@ static bool superh_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 +int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUSH4State *env =3D cpu_env(cs); + + /* + * The instruction in a RTE delay slot is fetched in privileged mode, + * but executed in user mode. + */ + if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { + return 0; + } else { + return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; + } +} + static void superh_cpu_reset_hold(Object *obj) { CPUState *s =3D CPU(obj); @@ -266,6 +281,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; + cc->mmu_index =3D sh4_cpu_mmu_index; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; cc->get_pc =3D superh_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853238; cv=none; d=zohomail.com; s=zohoarc; b=hxXQbImTDDiEhXvhVxsiA39LGfALYoEHqDrq0xZrnjDLDfRQ2EkCRb/x+fGuVdWMvtAe7ZJGXnF5tzX1lXV5M1MWiyoVyR3frxscTuImYFRj5+vthQeWY38pWK/nEJ6psXTz5vsFSWUUQfpEzkDl2f3QQRVIxFO5xLcPw9H6ZYw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853238; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZopJS6n3q/61pFFTS+CrIcUuDwZWn1ir79UoNqgUhuU=; b=QtgztIv9QR16hZApjJPkNKHqbh1gNHJN1Eio6hlavXiv3N6rFNYFiealeY+RPmgUcC7fa2T96QZ5RcYdsQU+gTqV7krT5WgRBYOeSKq0lENjJB2WLYmvOdcdPK42Spr4xTQ6VDGPfD9/u2fzRM5XqZI4N2kDyiNsFCt4ZU1p2xw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853238226157.06583342755266; Thu, 1 Feb 2024 21:53:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSw-0001z6-4f; Fri, 02 Feb 2024 00:51:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSr-0001gp-Hp for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:49 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmSn-00022S-3G for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:49 -0500 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-5d8df2edd29so1400108a12.2 for ; Thu, 01 Feb 2024 21:51:44 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853104; x=1707457904; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZopJS6n3q/61pFFTS+CrIcUuDwZWn1ir79UoNqgUhuU=; b=C9p3YHOL5k3UCUN77HHDofI+KPDLWwjZqwB61H7Uuj7cvsKd6ZNFL43/p4rEDjeFGy OuvEjfmLK7r8nh9rzb9zw3LFcshHa+m59t+BNoMVd1XxSMmFJzhWJyoU1YB8s3Vw0ftU ZxwmA8pL00EULvMuPvm/PbnsuSYN4wQiSj0xlHxQYs4JVRhjWGDPANwJ+OhrT+TUorJ6 JwOw4c8FGXzzWG/gt675gqq+cTUUAGCWhdvA571egKC4Wc29cBMp2reUt7Pj1dHddklX TORIc5uOb/7fOLNPQd7VNU3sDhIFhS3ZHeQpkNy78sDzlb0Aaeyq9WKaRVG3HFVLGyJY 3Bzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853104; x=1707457904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZopJS6n3q/61pFFTS+CrIcUuDwZWn1ir79UoNqgUhuU=; b=hBN8gJq1dx8PgDMYxdWK8IDVkBNXzHIV2uaavZWLgcGd/4cXMccLaWX8aBBaGuj61R KCL/ZIX75sZO17C7GPQV4jlu+4lPVQBqccIEkMv53rMbTl1MoTict8bYPHO2NzDy9SH9 s2wN4xkIS2ySj4FErkKK1P8CVzvEaWCuODMMW+5nclvnBY5OW0ERJULP1uPbW2KMBFoG cmvzdgwZINJSlp65/FZj2jEYGKbe24jm++F+eZBITbbzT1vmGs1XOXMF5SaRKCJZdYvG FxbGiCc05ogPIT0Mzl4KWqmVnynhMgZZz3KBOZK14dqWLHB78wsHajsYscG0/iBqiBFd I5MA== X-Gm-Message-State: AOJu0YyBv2U8jhk/AwguHuU6dmcf4vbAzvNWJXBx1x5CnIcuMhf5Z/jZ zMkSAAIG08tmMoz7vT96huZOky1Hg+1KaNsSR0ip5vaW0NwCerujjUkykpVCrDNcGAS/w8YAaZ3 MQb4= X-Google-Smtp-Source: AGHT+IHJ4s5JkbRIYBtmn1Xz6YrULqQCBjObvQu9XNv7psD2u/8bZpvhBrnxZCCp4CepXGrYfYQOdw== X-Received: by 2002:a05:6a20:1e60:b0:19e:3343:43c4 with SMTP id cy32-20020a056a201e6000b0019e334343c4mr4350156pzb.36.1706853103931; Thu, 01 Feb 2024 21:51:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 29/57] target/sparc: Populate CPUClass.mmu_index Date: Fri, 2 Feb 2024 15:50:08 +1000 Message-Id: <20240202055036.684176-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853238744100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 34 ++++++---------------------------- target/sparc/cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 28 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 12a11ecb26..92c58c92c1 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -708,34 +708,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *e= nv1) } #endif =20 -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ -#if defined(CONFIG_USER_ONLY) - return MMU_USER_IDX; -#elif !defined(TARGET_SPARC64) - if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ - return MMU_PHYS_IDX; - } else { - return env->psrs; - } -#else - /* IMMU or DMMU disabled. */ - if (ifetch - ? (env->lsu & IMMU_E) =3D=3D 0 || (env->pstate & PS_RED) !=3D 0 - : (env->lsu & DMMU_E) =3D=3D 0) { - return MMU_PHYS_IDX; - } else if (cpu_hypervisor_mode(env)) { - return MMU_PHYS_IDX; - } else if (env->tl > 0) { - return MMU_NUCLEUS_IDX; - } else if (cpu_supervisor_mode(env)) { - return MMU_KERNEL_IDX; - } else { - return MMU_USER_IDX; - } -#endif -} - static inline int cpu_interrupts_enabled(CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) @@ -777,6 +749,12 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 =20 +int sparc_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) +{ + return sparc_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflag= s) { diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 7d0d629a3d..7a3b815737 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -718,6 +718,34 @@ static bool sparc_cpu_has_work(CPUState *cs) cpu_interrupts_enabled(env); } =20 +int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUSPARCState *env =3D cpu_env(cs); + +#ifndef TARGET_SPARC64 + if ((env->mmuregs[0] & MMU_E) =3D=3D 0) { /* MMU disabled */ + return MMU_PHYS_IDX; + } else { + return env->psrs; + } +#else + /* IMMU or DMMU disabled. */ + if (ifetch + ? (env->lsu & IMMU_E) =3D=3D 0 || (env->pstate & PS_RED) !=3D 0 + : (env->lsu & DMMU_E) =3D=3D 0) { + return MMU_PHYS_IDX; + } else if (cpu_hypervisor_mode(env)) { + return MMU_PHYS_IDX; + } else if (env->tl > 0) { + return MMU_NUCLEUS_IDX; + } else if (cpu_supervisor_mode(env)) { + return MMU_KERNEL_IDX; + } else { + return MMU_USER_IDX; + } +#endif +} + static char *sparc_cpu_type_name(const char *cpu_model) { char *name =3D g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model); @@ -906,6 +934,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; cc->has_work =3D sparc_cpu_has_work; + cc->mmu_index =3D sparc_cpu_mmu_index; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853518; cv=none; d=zohomail.com; s=zohoarc; b=EcgkVX5eWomDkaJItKmGhA3hZgByLSPrUj71D8CmCB8PjRUItajz6uR7Eu8SB9+Yi9BAKhHVwm02SsvY+nAWw5QHoa9UTK6s4YCtmywPDYdyDIXAOsf7t/Ja6a0bMDiGIkpw/gJV9CxSm4same8zthBIgz159Ilrw28TpiTAZAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853518; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mMDUR8YTjAtFg0favVwCF9fiRHHGxe41Pc5h5Qu3z9s=; b=lIVdvCTMKosfgR6fLLVWVL7tYdQxLgbkHnV59ZAL1cd3jzOcCH7/J9TseD+iI4RDmq6h8Z3qF8zII52Kd5lHkx65tquhOaBHTOtkElG9/d2uR7Ww4byNZ3IJjTnto2mmboTZtdY+CywWA0KYHq5VKsUQZ3sP6Jy3CYs4AzDopDg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853518490344.106507379234; Thu, 1 Feb 2024 21:58:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmSu-0001q9-HI; Fri, 02 Feb 2024 00:51:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSr-0001gH-Gv for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:49 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmSp-000230-Bx for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:49 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6dddf4fc85dso1354927b3a.0 for ; Thu, 01 Feb 2024 21:51:46 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853519721100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/tricore/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e6d91c74b5..74e8a22b86 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -89,6 +89,11 @@ static bool tricore_cpu_has_work(CPUState *cs) return true; } =20 +static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return 0; +} + static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -194,6 +199,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) &mcc->parent_phases); cc->class_by_name =3D tricore_cpu_class_by_name; cc->has_work =3D tricore_cpu_has_work; + cc->mmu_index =3D tricore_cpu_mmu_index; =20 cc->gdb_read_register =3D tricore_cpu_gdb_read_register; cc->gdb_write_register =3D tricore_cpu_gdb_write_register; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853354; cv=none; d=zohomail.com; s=zohoarc; b=e5P9eSVWODE4OIi/P83ogfWXT4fkdS4u3OEw5+xD0buoVjI0mFO9S5drXbAcl9H3tksXsP2IJ/7VjRMobt5ickGSDG/VlkeBhuW3PxvUxhECvJeijCTEeyIT9ZUl4Ukk83bL7tTpRXrQaP8Hd0df8YykHjTt2Rs53cgoXNxCctM= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853355223100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/xtensa/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 62020b1f33..79f91819df 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -74,6 +74,11 @@ static bool xtensa_cpu_has_work(CPUState *cs) #endif } =20 +static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return xtensa_get_cring(cpu_env(cs)); +} + #ifdef CONFIG_USER_ONLY static bool abi_call0; =20 @@ -252,6 +257,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; + cc->mmu_index =3D xtensa_cpu_mmu_index; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; cc->get_pc =3D xtensa_cpu_get_pc; --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853316; cv=none; d=zohomail.com; s=zohoarc; b=MqPqj2w74Y7ILB99C1eJr5LtlGV4klZLiQQzyYtwgI8OFyxWsOG0ebaqVVW3OrmyhA6r03mG7axuz0n/yt6oUg16vrN87OkmJLynUJ+oI1t6vaay6GJL2NW3zuBZfv+BQBLiviOke/kcJzBPc1OLJraeys1liiIRJWNeSZ82pCM= ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853110; x=1707457910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K2jrfQ38ow0bP4d/lUq0tcSuA+PB2DtmVKU7EqqTHAY=; b=DJoYNnaNKtJkHJA/bnsKQruE84Ga02TMjTN+xSrzSWXzfIdENA5X8Up4T3uul9kLkE knouIYJS1s5QZYPWhRVnz0ATYnhcXeDA1up3Ik9AO6zmXM8476si9K2AMY5mcXWUtcTg LQdxjgkDKsr12mRn553xkl5xTP1iNoPYEb38qEZXQdZveoUfQEvt5lBBAdM9KmMMLVVx SdlbSASVY3ktxDJnyzR9Ig+DQ2yr5cvOaypF792NrmUFWNz64O6Lf7JkVREe9en5V7p5 VCAuloB0xNmImr2qjeOsSaaCi1xlB81we8I3/gAxtZQFFpUuLt4vGIC+nETFZXkJw9dU uevw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853110; x=1707457910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K2jrfQ38ow0bP4d/lUq0tcSuA+PB2DtmVKU7EqqTHAY=; b=g4phnJ7VFsf7Pd676wQ3dpdoIxZiYSZFrc5TnkYFHrbeTRLjX+gXWeMQtBgWbX88ii REqy27y/JeG9LWcTtpbGzSup3hAqanpIiWJbFo5iOLROEbwdWUz65ilqphmtf5nxiu5N lXD2DzyuvB3GL1KuxY2HKSiA2E2g53Xbhf9aFyE/9hSsdZh7WPwYF1T+gG9c8QrAPl0d T/NXdB875PE0b8XWG+lINFwHNuX/qh9EVLkuayJbb32v7TWxmtfxVALYhA5qfpRXRp/y nryEVyqlTvcn6ahEnx4S2FYGxI1wskotsGjO/7wJhRKJTPvcL+EVZyO8j+nF8ukfCf5Y oxHA== X-Gm-Message-State: AOJu0YzFKkTEEm0w8C3GWCalJGKmka/As4NXQRmyeB0JwG/63IPBgCcc tT3/5Mj62aeuah4gjVrHR0A+aQ6ePr1p3bjnleSpAsqccUNZ64XQrz5+DXJdqeyVEXBkH63Gskz K3II= X-Google-Smtp-Source: AGHT+IExs0s6+P+jFb6+XR6W95eoE4LfcsVLZtJs9ZDYC0dIdVPUWPzXWZk6E+elq23LckAW1ASOig== X-Received: by 2002:a05:6a20:2d10:b0:19c:9c76:e9b2 with SMTP id g16-20020a056a202d1000b0019c9c76e9b2mr2114473pzl.13.1706853110280; Thu, 01 Feb 2024 21:51:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 32/57] include/exec: Implement cpu_mmu_index generically Date: Fri, 2 Feb 2024 15:50:11 +1000 Message-Id: <20240202055036.684176-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853317010100001 For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 ++++ include/exec/cpu-common.h | 22 ++++++++++++++++++++++ target/alpha/cpu.h | 5 ----- target/arm/cpu.h | 13 ------------- target/avr/cpu.h | 5 ----- target/cris/cpu.h | 4 ---- target/hexagon/cpu.h | 9 --------- target/hppa/cpu.h | 10 ---------- target/i386/cpu.h | 6 ------ target/loongarch/cpu.h | 10 ---------- target/m68k/cpu.h | 4 ---- target/microblaze/cpu.h | 6 ------ target/mips/cpu.h | 5 ----- target/nios2/cpu.h | 6 ------ target/openrisc/cpu.h | 6 ------ target/ppc/cpu.h | 5 ----- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 5 ----- target/s390x/cpu.h | 2 -- target/sh4/cpu.h | 6 ------ target/sparc/cpu.h | 6 ------ target/tricore/cpu.h | 5 ----- target/xtensa/cpu.h | 5 ----- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- 31 files changed, 34 insertions(+), 133 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8501a33dbf..80c0d0699b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -311,6 +311,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) #define TLB_WATCHPOINT 0 =20 +static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +{ + return MMU_USER_IDX; +} #else =20 /* diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index dcbd5f5783..cdfbe994fd 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -8,6 +8,7 @@ #include "exec/hwaddr.h" #endif #include "hw/core/cpu.h" +#include "tcg/debug-assert.h" =20 #define EXCP_INTERRUPT 0x10000 /* async interruption */ #define EXCP_HLT 0x10001 /* hlt instruction reached */ @@ -262,4 +263,25 @@ static inline CPUState *env_cpu(CPUArchState *env) return (void *)env - sizeof(CPUState); } =20 +#ifndef CONFIG_USER_ONLY +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + * + * The user-only version of this function is inline in cpu-all.h, + * where it always returns MMU_USER_IDX. + */ +static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +{ + CPUState *cs =3D env_cpu(env); + int ret =3D cs->cc->mmu_index(cs, ifetch); + tcg_debug_assert(ret >=3D 0 && ret < NB_MMU_MODES); + return ret; +} +#endif /* !CONFIG_USER_ONLY */ + #endif /* CPU_COMMON_H */ diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 3beff2738a..7188a409a0 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -398,11 +398,6 @@ static inline int alpha_env_mmu_index(CPUAlphaState *e= nv) return ret; } =20 -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) -{ - return alpha_env_mmu_index(env); -} - enum { IR_V0 =3D 0, IR_T0 =3D 1, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d3477b1601..63f31e0d98 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3240,19 +3240,6 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHIC= H) =20 -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - return EX_TBFLAG_ANY(env->hflags, MMUIDX); -} - /** * sve_vq * @env: the cpu context diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4595c6bb18..d185d20dcb 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,11 +184,6 @@ static inline void set_avr_feature(CPUAVRState *env, i= nt feature) env->features |=3D (1U << feature); } =20 -static inline int cpu_mmu_index(CPUAVRState *env, bool ifetch) -{ - return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; -} - void avr_cpu_tcg_init(void); =20 int cpu_avr_exec(CPUState *cpu); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d830dcac5b..3904e5448c 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -260,10 +260,6 @@ enum { =20 /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) -{ - return !!(env->pregs[PR_CCS] & U_FLAG); -} =20 /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 5c11ae3445..3eef58fe8f 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -146,15 +146,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonStat= e *env, vaddr *pc, *flags =3D hex_flags; } =20 -static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else -#error System mode not supported on Hexagon yet -#endif -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 04439f247d..7a181e8f33 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -281,16 +281,6 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; } =20 -int hppa_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return hppa_cpu_mmu_index(env_cpu(env), ifetch); -#endif -} - void hppa_translate_init(void); =20 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 62bdb02378..6a5b180ccb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2315,12 +2315,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) #include "hw/i386/apic.h" #endif =20 -int x86_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return x86_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 47fd110e81..ec37579fd6 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -408,16 +408,6 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 =20 -int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return loongarch_cpu_mmu_index(env_cpu(env), ifetch); -#endif -} - static inline bool is_la64(CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index d13427b0fe..aca4aa610b 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -577,10 +577,6 @@ enum { /* MMU modes definitions */ #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) -{ - return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; -} =20 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 90ab796de9..446af5dd4c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -434,12 +434,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr ph= ysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 -int mb_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) -{ - return mb_cpu_mmu_index(env_cpu(env), ifetch); -} - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4c15e76781..ef26fe03c7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1260,11 +1260,6 @@ static inline int mips_env_mmu_index(CPUMIPSState *e= nv) return hflags_mmu_index(env->hflags); } =20 -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) -{ - return mips_env_mmu_index(env); -} - #include "exec/cpu-all.h" =20 /* Exceptions */ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 9965ff74c1..4164a3432e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -286,12 +286,6 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 =3D=3D 0. */ =20 -int nios2_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return nios2_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 7dbed8d8be..b1b7db5cbd 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,12 +361,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCSta= te *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } =20 -int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) -{ - return openrisc_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5f4f52aec5..a44de22ca4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1633,11 +1633,6 @@ static inline int ppc_env_mmu_index(CPUPPCState *env= , bool ifetch) #endif } =20 -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) -{ - return ppc_env_mmu_index(env, ifetch); -} - /* Compatibility modes */ #if defined(TARGET_PPC64) bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9c825c7b51..f63ee9cc58 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -507,8 +507,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); =20 -#define cpu_mmu_index riscv_env_mmu_index - #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 65f9cd2d0a..c53593d7aa 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -158,11 +158,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *en= v, vaddr *pc, *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); } =20 -static inline int cpu_mmu_index(CPURXState *env, bool ifetch) -{ - return 0; -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index f0fed5d6ad..d37a49b4d9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -412,8 +412,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *en= v, bool ifetch) #endif } =20 -#define cpu_mmu_index s390x_env_mmu_index - #ifdef CONFIG_TCG =20 #include "tcg/tcg_s390x.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9c5e2b349e..9211da6bde 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -370,12 +370,6 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -int sh4_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUSH4State *env, bool ifetch) -{ - return sh4_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 92c58c92c1..51856152fa 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -749,12 +749,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 =20 -int sparc_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ - return sparc_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflag= s) { diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 2d4446cea5..220af69fc2 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -246,11 +246,6 @@ void fpu_set_state(CPUTriCoreState *env); =20 #define MMU_USER_IDX 2 =20 -static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) -{ - return 0; -} - #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, PRIV, 0, 2) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4b033ee924..6b8d0636d2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -713,11 +713,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) /* MMU modes definitions */ #define MMU_USER_IDX 3 =20 -static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) -{ - return xtensa_get_cring(env); -} - #define XTENSA_TBFLAG_RING_MASK 0x3 #define XTENSA_TBFLAG_EXCM 0x4 #define XTENSA_TBFLAG_LITBASE 0x8 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index fbb37e541e..5f87c1b12a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -94,7 +94,7 @@ static bool hppa_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 -int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) +static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUHPPAState *env =3D cpu_env(cs); =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 280bcb7d00..ef46755a50 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7720,7 +7720,7 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; } =20 -int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUX86State *env =3D cpu_env(cs); =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 139acfe373..b08d0dc5de 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -375,7 +375,7 @@ static bool loongarch_cpu_has_work(CPUState *cs) #endif } =20 -int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) { CPULoongArchState *env =3D cpu_env(cs); =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6dad11905b..2002231a6b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -118,7 +118,7 @@ static bool mb_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); } =20 -int mb_cpu_mmu_index(CPUState *cs, bool ifetch) +static int mb_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUMBState *env =3D cpu_env(cs); MicroBlazeCPU *cpu =3D env_archcpu(env); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e42885997e..0760bf6b38 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -57,7 +57,7 @@ static bool nios2_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 -int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) +static int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) { return (cpu_env(cs)->ctrl[CR_STATUS] & CR_STATUS_U ? MMU_USER_IDX : MMU_SUPERVISOR_IDX); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 8670152c84..a3cb80ca34 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -68,7 +68,7 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } =20 -int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUOpenRISCState *env =3D cpu_env(cs); =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 6fead5655f..2031168dc6 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -89,7 +89,7 @@ static bool superh_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 -int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUSH4State *env =3D cpu_env(cs); =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 7a3b815737..afa62723fe 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -718,7 +718,7 @@ static bool sparc_cpu_has_work(CPUState *cs) cpu_interrupts_enabled(env); } =20 -int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUSPARCState *env =3D cpu_env(cs); =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853426; cv=none; d=zohomail.com; s=zohoarc; b=hlvAkWKp4NpHl1LZbqS1j7TDZqci/7ShPN4ScfIOqh/rM2vgAWTp5cangiEmcYPb/mMJYm6PaNqVDMHEF9Cbe40aG7WYZkvntch7cA7oO72YfmFU/g09Oi8Wv/RM+1nbktTTJCKCktIxShNrpt9vwsYy+rg5oRuG2iA3Whv+NgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853426; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=V5DcaABDb9a5Acv7c8zuGNE7yRin2rz8nKGTze/VBOM=; b=RaCCbXZUEicOFnXeQpSZL8M6W8jOpTrtNzOZ2ceSzhzweRcGtSyCGxrP1vt7DwgVd6LyACITjntdwCmpA8jBlwmeSvtV3hU6X8W+sFtILwfZ7yiI8F3g9MCEH82Fe9IdfEQIdJ0AWapIzhpJnP1yJroccCBYM+CJY7kuk4Ch7ZU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853426835277.73303131379873; Thu, 1 Feb 2024 21:57:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmT1-0002Od-3s; Fri, 02 Feb 2024 00:51:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmSy-000283-HN for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:56 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmSv-00025r-OH for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:56 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6ddc268ce2bso1069207b3a.0 for ; Thu, 01 Feb 2024 21:51:53 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853427521100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 +- include/exec/cpu-common.h | 3 +-- target/sparc/cpu.h | 2 +- accel/tcg/cputlb.c | 22 +++++++++------- semihosting/uaccess.c | 2 +- target/cris/translate.c | 2 +- target/hppa/mem_helper.c | 2 +- target/hppa/op_helper.c | 8 +++--- target/i386/tcg/translate.c | 2 +- target/loongarch/tcg/tlb_helper.c | 4 +-- target/m68k/op_helper.c | 2 +- target/microblaze/helper.c | 3 +-- target/microblaze/mmu.c | 2 +- target/microblaze/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/sparc/ldst_helper.c | 2 +- target/sparc/mmu_helper.c | 2 +- target/tricore/helper.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/mmu_helper.c | 2 +- accel/tcg/ldst_common.c.inc | 42 ++++++++++++++++++++----------- 22 files changed, 65 insertions(+), 49 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 80c0d0699b..bc05dce7ab 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -311,7 +311,7 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) #define TLB_WATCHPOINT 0 =20 -static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +static inline int cpu_mmu_index(CPUState *cs, bool ifetch) { return MMU_USER_IDX; } diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index cdfbe994fd..9ead1be100 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -275,9 +275,8 @@ static inline CPUState *env_cpu(CPUArchState *env) * The user-only version of this function is inline in cpu-all.h, * where it always returns MMU_USER_IDX. */ -static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +static inline int cpu_mmu_index(CPUState *cs, bool ifetch) { - CPUState *cs =3D env_cpu(env); int ret =3D cs->cc->mmu_index(cs, ifetch); tcg_debug_assert(ret >=3D 0 && ret < NB_MMU_MODES); return ret; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 51856152fa..1e076f6355 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -755,7 +755,7 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *= env, vaddr *pc, uint32_t flags; *pc =3D env->pc; *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env, false); + flags =3D cpu_mmu_index(env_cpu(env), false); #ifndef CONFIG_USER_ONLY if (cpu_supervisor_mode(env)) { flags |=3D TB_FLAG_SUPER; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3facfcbb24..047cd2cc0a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1601,7 +1601,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, vaddr addr, void *p; =20 (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), false, + cpu_mmu_index(env_cpu(env), true), false, &p, &full, 0, false); if (p =3D=3D NULL) { return -1; @@ -2959,26 +2959,30 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, = Int128 val, =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(env, true)); - return do_ld1_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(cs, true)); + return do_ld1_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); - return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true)); + return do_ld2_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); - return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true)); + return do_ld4_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); - return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true)); + return do_ld8_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index 5d889f9263..dc587d73bc 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -26,7 +26,7 @@ void *uaccess_lock_user(CPUArchState *env, target_ulong a= ddr, =20 ssize_t uaccess_strlen_user(CPUArchState *env, target_ulong addr) { - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), false); size_t len =3D 0; =20 while (1) { diff --git a/target/cris/translate.c b/target/cris/translate.c index 7acea29a01..8f74b6c53f 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -2966,7 +2966,7 @@ static void cris_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) dc->cpu =3D env_archcpu(env); dc->ppc =3D pc_start; dc->pc =3D pc_start; - dc->mem_index =3D cpu_mmu_index(env, false); + dc->mem_index =3D cpu_mmu_index(cs, false); dc->flags_uptodate =3D 1; dc->flags_x =3D tb_flags & X_FLAG; dc->cc_x_uptodate =3D 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 4fcc612754..629a9d90ef 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -646,7 +646,7 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulon= g vaddr) void HELPER(diag_btlb)(CPUHPPAState *env) { unsigned int phys_page, len, slot; - int mmu_idx =3D cpu_mmu_index(env, 0); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); uintptr_t ra =3D GETPC(); HPPATLBEntry *btlb; uint64_t virt_page; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index ce15469465..b1f24a5aad 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -59,7 +59,7 @@ void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { - int mmu_idx =3D cpu_mmu_index(env, 0); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); uint32_t old, new, cmp, *haddr; void *vaddr; =20 @@ -86,7 +86,7 @@ static void atomic_store_mask64(CPUHPPAState *env, target= _ulong addr, int size, uintptr_t ra) { #ifdef CONFIG_ATOMIC64 - int mmu_idx =3D cpu_mmu_index(env, 0); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); uint64_t old, new, cmp, *haddr; void *vaddr; =20 @@ -235,7 +235,7 @@ static void do_stby_e(CPUHPPAState *env, target_ulong a= ddr, target_ulong val, default: /* Nothing is stored, but protection is checked and the cacheline is marked dirty. */ - probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); + probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra); break; } } @@ -296,7 +296,7 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong = addr, uint64_t val, default: /* Nothing is stored, but protection is checked and the cacheline is marked dirty. */ - probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); + probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra); break; } } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2808903661..10cba16256 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6955,7 +6955,7 @@ static void i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) dc->cc_op_dirty =3D false; dc->popl_esp_hack =3D 0; /* select memory access functions */ - dc->mem_index =3D cpu_mmu_index(env, false); + dc->mem_index =3D cpu_mmu_index(cpu, false); dc->cpuid_features =3D env->features[FEAT_1_EDX]; dc->cpuid_ext_features =3D env->features[FEAT_1_ECX]; dc->cpuid_ext2_features =3D env->features[FEAT_8000_0001_EDX]; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 65ffbef08e..9e2a44c119 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -241,7 +241,7 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) int prot; =20 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D 0) { + cpu_mmu_index(cs, false)) !=3D 0) { return -1; } return phys_addr; @@ -320,7 +320,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) uint8_t tlb_ps; LoongArchTLB *tlb =3D &env->tlb[index]; =20 - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), false); uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); uint8_t tlb_v1 =3D FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 1ce850bbc5..47b4173bb9 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -811,7 +811,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2, uint32_t l1, l2; uintptr_t ra =3D GETPC(); #if defined(CONFIG_ATOMIC64) - int mmu_idx =3D cpu_mmu_index(env, 0); + int mmu_idx =3D cpu_mmu_index(env_cpu(env), 0); MemOpIdx oi =3D make_memop_idx(MO_BEUQ, mmu_idx); #endif =20 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..460eee0cf5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -228,10 +228,9 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, = vaddr addr, MemTxAttrs *attrs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); - CPUMBState *env =3D &cpu->env; target_ulong vaddr, paddr =3D 0; MicroBlazeMMULookup lu; - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D cpu_mmu_index(cs, false); unsigned int hit; =20 /* Caller doesn't initialize */ diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 75651979a9..234006634e 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -305,7 +305,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) } =20 hit =3D mmu_translate(cpu, &lu, v & TLB_EPN_MASK, - 0, cpu_mmu_index(env, false)); + 0, cpu_mmu_index(env_cpu(env), false)); if (hit) { env->mmu.regs[MMU_R_TLBX] =3D lu.idx; } else { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2e628647d1..a465c2d245 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1607,7 +1607,7 @@ static void mb_tr_init_disas_context(DisasContextBase= *dcb, CPUState *cs) dc->ext_imm =3D dc->base.tb->cs_base; dc->r0 =3D NULL; dc->r0_set =3D false; - dc->mem_index =3D cpu_mmu_index(&cpu->env, false); + dc->mem_index =3D cpu_mmu_index(cs, false); dc->jmp_cond =3D dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NE= VER; dc->jmp_dest =3D -1; =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 3078372b36..612556b297 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -948,7 +948,7 @@ static void nios2_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) Nios2CPU *cpu =3D env_archcpu(env); int page_insns; =20 - dc->mem_idx =3D cpu_mmu_index(env, false); + dc->mem_idx =3D cpu_mmu_index(cs, false); dc->cr_state =3D cpu->cr_state; dc->tb_flags =3D dc->base.tb->flags; dc->eic_present =3D cpu->eic_present; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d4cbc5eaea..785bcb6552 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1528,7 +1528,7 @@ static void openrisc_tr_init_disas_context(DisasConte= xtBase *dcb, CPUState *cs) CPUOpenRISCState *env =3D cpu_env(cs); int bound; =20 - dc->mem_idx =3D cpu_mmu_index(env, false); + dc->mem_idx =3D cpu_mmu_index(cs, false); dc->tb_flags =3D dc->base.tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; dc->cpucfgr =3D env->cpucfgr; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..52aa6c631b 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -690,7 +690,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong= addr, case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ break; case ASI_KERNELTXT: /* Supervisor code access */ - oi =3D make_memop_idx(memop, cpu_mmu_index(env, true)); + oi =3D make_memop_idx(memop, cpu_mmu_index(env_cpu(env), true)); switch (size) { case 1: ret =3D cpu_ldb_code_mmu(env, addr, oi, GETPC()); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..5170a668bb 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -901,7 +901,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; hwaddr phys_addr; - int mmu_idx =3D cpu_mmu_index(env, false); + int mmu_idx =3D cpu_mmu_index(cs, false); =20 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) !=3D 0)= { if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != =3D 0) { diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 174f666e1e..649373a9cb 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -48,7 +48,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) TriCoreCPU *cpu =3D TRICORE_CPU(cs); hwaddr phys_addr; int prot; - int mmu_idx =3D cpu_mmu_index(&cpu->env, false); + int mmu_idx =3D cpu_mmu_index(cs, false); =20 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, MMU_DATA_LOAD, mmu_idx)) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index f1156c39e7..278c514ab0 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8355,7 +8355,7 @@ static void tricore_tr_init_disas_context(DisasContex= tBase *dcbase, { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUTriCoreState *env =3D cpu_env(cs); - ctx->mem_idx =3D cpu_mmu_index(env, false); + ctx->mem_idx =3D cpu_mmu_index(cs, false); =20 uint32_t tb_flags =3D (uint32_t)ctx->base.tb->flags; ctx->priv =3D FIELD_EX32(tb_flags, TB_FLAGS, PRIV); diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 2fda4e887c..47063b0a57 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -66,7 +66,7 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t = vaddr) * only the side-effects (ie any MMU or other exception) */ probe_access(env, vaddr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), GETPC()); + cpu_mmu_index(env_cpu(env), true), GETPC()); } =20 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 44833513fb..c82048e377 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -354,7 +354,8 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint64_t val, =20 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra); } =20 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -364,7 +365,8 @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, u= intptr_t ra) =20 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra); } =20 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -374,17 +376,20 @@ int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ad= dr, uintptr_t ra) =20 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra); } =20 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra); } =20 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra); } =20 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -394,54 +399,63 @@ int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ad= dr, uintptr_t ra) =20 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra); } =20 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra); } =20 void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_t ra) { - cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_t ra) { - cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 /*--------------------------*/ --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853114; x=1707457914; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vVBvMUdV2y5YTBfcwLaxMR/FCDaPatuMxQEr9twVZ58=; b=dX3VzSusWEkCgUa/O/PzpYWdkRaLI7czUC2/HhPhVGHSV8aLGnce1mAFmQoxD+Hdsg eUanpu92U4M4YupjtLuvGwLipSCG+olri0b1XFbVMKnJqYqDpW/R3tlT9324dwuW8pWW CXDrBmptVVQ5VzJxMx2OvcmWdVfUlFLcT5y/8uAztPZha7A1SiZrM/DyTgbTEQohavEE ssh7DptjkO6EwrEIATXY9TKeVySckThhMgbDsejyuDX9EHR7wBc2d562xNLSvUwQbPRd sbnWKnT/TB7gm0I/LyWv/T+JRXyQoles1DRpmhUNa+sBlHxzhjlVaH32qT8OHV6UIj56 7ktg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853114; x=1707457914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vVBvMUdV2y5YTBfcwLaxMR/FCDaPatuMxQEr9twVZ58=; b=hK+t6QpbXe7QmdQjFeVNFR5gHEUyjxOkZYQpKEYJodAfvgpPe2TH1J1HGoSHKSVN+s R0e7afqLKZW+HBszPZKlVCEi9EEH4mf54sTJ9z/4MJo9n2gksGiBg3IWphV25wORjWF0 kYBKGA4Vs9fgTD8gEdJa2aQtqmk/GT2gjnYCEfH/DCevImlfepRH8PEt5AykqTh4o+NL cCKJGpBItw+87pBAcjFP1FaT66OdA0Cqxk/UBpv85kTBXOUEB73uYEG9JT7JCL+KhE+M 0vj3Ougshj5yED46mSHg6sSOkd28u2hWjFmwg78CtgNW+xmKic0jj3JJMAr0T7ETtnMd iUAA== X-Gm-Message-State: AOJu0YwSz9Y4FhfkfVP3NnV2AndguOHSD2ULJC7dY0v1K3HkAdV4IdVO Wq7tb4vZyg1HdIGOZYZ/vXFKl8Xfcux0bKa9wnQVsihc42+tx+YG3TvHeqoFvHKQd+5w62mdHzl +NL4= X-Google-Smtp-Source: AGHT+IH+3EqlMUXcqpwAHRpFFo7sCd1J0Ih23UbXmfaLoh0ZS7v3BZp0r2MlwQMzOjyoDPbQgxcK/g== X-Received: by 2002:a05:6808:1889:b0:3bf:bcba:6d57 with SMTP id bi9-20020a056808188900b003bfbcba6d57mr1673498oib.41.1706853114422; Thu, 01 Feb 2024 21:51:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PULL 34/57] tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test Date: Fri, 2 Feb 2024 15:50:13 +1000 Message-Id: <20240202055036.684176-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853413490100008 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich The `if not probe_proc_self_mem` check never passes, because probe_proc_self_mem is a function object, which is a truthy value. Add parentheses in order to perform a function call. Fixes: dc84d50a7f9b ("tests/tcg: Add the PROT_NONE gdbstub test") Signed-off-by: Ilya Leoshkevich Message-Id: <20240131220245.235993-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/multiarch/gdbstub/prot-none.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/multiarch/gdbstub/prot-none.py b/tests/tcg/multiarch= /gdbstub/prot-none.py index e829d3ebc5..7e264589cb 100644 --- a/tests/tcg/multiarch/gdbstub/prot-none.py +++ b/tests/tcg/multiarch/gdbstub/prot-none.py @@ -20,7 +20,7 @@ def probe_proc_self_mem(): =20 def run_test(): """Run through the tests one by one""" - if not probe_proc_self_mem: + if not probe_proc_self_mem(): print("SKIP: /proc/self/mem is not usable") exit(0) gdb.Breakpoint("break_here") --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853180; cv=none; d=zohomail.com; s=zohoarc; b=m6jmWfX2IPYOue7bMn7ZpoBk9yMM+6Ms9YnADXm3Deos1RKSGNazfRvB0/mxQBftMffhLDLELPtlRppyXMjDOWip9spXA4jQMjLLLn7hPxEur2awYFtKjc8iOz5fRIJ5lwBvgrcQSoqRiXSRZEMMF0dxCqdU54jGKXlkl94/NdA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853180; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=enqyHM/qlHAKrvGyjKOBiar72kS5zHVgEoJYNNdlxDQ=; b=TcjbCt0/3keJnBd2uYi0xiZ0Bo3uFogn7WTkQ6IBP6aTBxFNrpDpbh/8VlMcKCjZU8GNHqXh6LFzzpWFDbFqbmXCWXhVVvoLllQ/typsnyeqqnt4qa+sTBTgiLTx3zbLpWDQtDBfvYlhdPk5P2i0NO5Hams9stjyKgPvukE3NtU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853180783110.86150656317432; Thu, 1 Feb 2024 21:53:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmT5-0002o4-HQ; Fri, 02 Feb 2024 00:52:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmT1-0002UZ-UX for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:59 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmT0-00027i-2a for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:51:59 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6ddfb0dac4dso1335739b3a.1 for ; Thu, 01 Feb 2024 21:51:57 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853117; x=1707457917; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=enqyHM/qlHAKrvGyjKOBiar72kS5zHVgEoJYNNdlxDQ=; b=JXxiM572DonvC6pArZSCdO9ss2EdgaYX4Oby+VV0dfvqEkVm74IoH7KEh9wVPoS9j/ 7Ekb5ehy+NIntaYl09LA8WnbT+uQQjKoT2sjz8Q9yvqkykYqEhmV/N9h0oHgO87k3gyz NDvWwtsxYJN7a95y6cZYbQiXjVpOxwguSFm1/qNv0JvNXZRJSZIrtc13YwQc38QZvQax UEW46OzHK0117lMBDVlcZaa/UDvDX4qfl8bS8RxiWchOp4SYsBwfrZieBW5Kj3PghsOR AWckP7Yv6Td27j2FHeb/Rfh3HwxJFlR51gFRse025uqcB3T/4aOosIwuHbVza5CuVTsd drMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853117; x=1707457917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=enqyHM/qlHAKrvGyjKOBiar72kS5zHVgEoJYNNdlxDQ=; b=oYVWoxCVT3Vgx9bFJCWG8ztqbAil6U4w/xIa/CmZ+ll7EM/TjwQII8bgDIeaOkFBDT 8HxPf/npsUlryTf9jG8sTCDXVHnyuQasv8ZUQSECs72TPyeFCviIms4s1EV9xtMPdXWG 5fqzQVme/rKhVCMMR2EbrYrN34XGl8d/EyZQNBT5CDfkwgQr5yJWwZr6gJgjda5LRsr2 WV8R7tXyPn/ONgQaPO3Z+lEMcS91OqhU5Wsj2/ZzfzkDXPKQnDHfOSEv1Wd5DbRg9P5+ ku94uDf94Opo0/O5gnxTthc6cI2d4clLDlP7/xBtMxkkG54GAtscWN0aC4fiUFdn6OCA dbjQ== X-Gm-Message-State: AOJu0Yz61p1Zg8ZECz5gTo9AUBLAE08oRAOaTdOozH776ujZWpwuPraC pFG4B8aFHb9MLCTrkmfZZqYqqBgfFAQPOB4p4ufya2wbX9PL6LINJxvYPS/i0Eq5zRK5zZ9TnlR nAV4= X-Google-Smtp-Source: AGHT+IGWY2ek1R607E9nacg77ESi2+0UNpHrIvzu5L90MyGCd9oJ+mgsclxBBOx/BbeEkuRARZ3ZEg== X-Received: by 2002:a05:6a00:23cb:b0:6db:d978:9047 with SMTP id g11-20020a056a0023cb00b006dbd9789047mr8634401pfc.1.1706853116815; Thu, 01 Feb 2024 21:51:56 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCVK//GlkMYx7LaQShTPiCXe/LPvnqxRn4jv2adJfhkGn5Na3Hy/8W+8VmaHIFaGC/PfEs492ETnUQkJMi9N5Pt/HVo2 From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Song Gao Subject: [PULL 35/57] tcg/loongarch64: Set vector registers call clobbered Date: Fri, 2 Feb 2024 15:50:14 +1000 Message-Id: <20240202055036.684176-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853182527100006 Content-Type: text/plain; charset="utf-8" Because there are more call clobbered registers than call saved registers, we begin with all registers as call clobbered and then reset those that are saved. This was missed when we introduced the LSX support. Cc: qemu-stable@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136 Signed-off-by: Richard Henderson Reviewed-by: Song Gao Message-Id: <20240201233414.500588-1-richard.henderson@linaro.org> --- tcg/loongarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index bab0a173a3..dcf0205458 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2327,7 +2327,7 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS; =20 - tcg_target_call_clobber_regs =3D ALL_GENERAL_REGS; + tcg_target_call_clobber_regs =3D ALL_GENERAL_REGS | ALL_VECTOR_REGS; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853411; cv=none; d=zohomail.com; s=zohoarc; b=NXxAHgwsSfKE92LjSc/ULqhsmTZ421iQTL/5OvhTUJzlcio3TtKxXt/sd0ZV5r5bE84Wvc4Bv7mbguYOPt0+vHLUSw3BbAPwC3oqvFcM5wmG3+k0F9gvhNu/4IyHUh4lpxMl2Cwj/B7f+KrOgE/8/hUMZLcr9KmnxoQxBAsYJ+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853411; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UsEJ2g0LpvdUYy2sbV8u3yNlPUAlmvtjJu3b7/RUdbU=; b=Zizodqw9xxLi8NLsXdMgDVV/mfZHPba93ULSjHgVMlgM6iH1ZN1O/7FK/rUhZVQ55h4lqvVPrgd1POXixe1hUfpDugQg3oCzF2y4LGR1pEPgjHKvonk+3MLiTk5XuNIjTxlpobbIvN5RI0LveUtPtIB6bxwJ4U2DthKU/73B35k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853411906279.26569560060034; Thu, 1 Feb 2024 21:56:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmT6-0002zw-FZ; Fri, 02 Feb 2024 00:52:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmT3-0002ks-Um for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:52:01 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmT2-00028J-4q for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:52:01 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6ddc1fad6ddso1462886b3a.0 for ; Thu, 01 Feb 2024 21:51:59 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853119; x=1707457919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UsEJ2g0LpvdUYy2sbV8u3yNlPUAlmvtjJu3b7/RUdbU=; b=sa/jom/Sl1nEyGR/1Rqq05zFugo2ObJAduqWhzQ5401X8H5UM7Zmslfy1T1HMw9HE3 MD+655gITkh3ZePcTUY8aMAx9WvUv3xXt7OfDDh0vk/vH5/PTNgBbDqn/+I1hSu8vN5r e832zS9tvNyPRs93YuAj0WrA/VWAim2dZo9eQaAUkEJK2/QzMQQpPdazuFxph5n+7r+O 5dY1Rb8ujo6FDd6TqL6n79EyZMPmZwnSfgygnfjzOKXGtM5O81xgOZn6aQL5kUJY2wC4 IUIOMfcKLpiqVJlXx6FeBA+fEmgs53P4qPBksjZTlqIukwzd5gs0bhf9AK7ufptTQlsO p+Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853119; x=1707457919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UsEJ2g0LpvdUYy2sbV8u3yNlPUAlmvtjJu3b7/RUdbU=; b=b1CqAcZlCQMsEhMRYRBwg1U8o7+JKmI/UxLYH90t6poe5oGL6k6yl4trBXit2ZzO82 9XzguV3zASa/SyiL/DYZwBZ7jkthgFXsKkEQBzNBONt4S/ZH2TjRjENyzrQVKIDCL1ed 5QckRaVS3/b1jta68b0IAyPs1rHzjs2zCHMquTSwCZ2MIXW11GTW9XAmDJg3gyLNH31K W0jAECHBOvHr1upfOrETAKz2uIyZc3ksDQhHggeXi+UkivfmdGYIULukahH1g5gjhWXw yZWtdC/3Br4+43Jo2e5KsT0qypUlrQDMg5jq9PW3ZtHFSdO8kvj0dgUCvsGq8bmroAA+ y3eQ== X-Gm-Message-State: AOJu0Yw1Jqk8YkUSYprtZw6yidLa770W47XMx2YRIhGeRuJyw4Xy9FwB LLAzJYFJ3koKihrh8dSLBqfYcUIa0QCU+2VDCVM4eHh7PuoZCVkWM2P3VoF9eYLxgQfC2g+b5P3 HTHw= X-Google-Smtp-Source: AGHT+IGVWnMN0S7UWXe2NedOWawYsbLtQSlXWXKbcT6d7BLH7/obx2ckMvkk8sIqAFBbgnzGyz45gA== X-Received: by 2002:a05:6a00:3cc9:b0:6dd:b12f:12ef with SMTP id ln9-20020a056a003cc900b006ddb12f12efmr5751673pfb.1.1706853118840; Thu, 01 Feb 2024 21:51:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 36/57] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY Date: Fri, 2 Feb 2024 15:50:15 +1000 Message-Id: <20240202055036.684176-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853413471100007 Content-Type: text/plain; charset="utf-8" Align the operation to the 32-byte cacheline. Use 2 pair of i128 instead of 8 pair of i32. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-2-richard.henderson@linaro.org> --- target/sparc/translate.c | 43 +++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 97184fa403..1082aabc14 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1727,28 +1727,35 @@ static void gen_st_asi(DisasContext *dc, DisasASI *= da, TCGv src, TCGv addr) =20 case GET_ASI_BCOPY: assert(TARGET_LONG_BITS =3D=3D 32); - /* Copy 32 bytes from the address in SRC to ADDR. */ - /* ??? The original qemu code suggests 4-byte alignment, dropping - the low bits, but the only place I can see this used is in the - Linux kernel with 32 byte alignment, which would make more sense - as a cacheline-style operation. */ + /* + * Copy 32 bytes from the address in SRC to ADDR. + * + * From Ross RT625 hyperSPARC manual, section 4.6: + * "Block Copy and Block Fill will work only on cache line boundar= ies." + * + * It does not specify if an unaliged address is truncated or trap= ped. + * Previous qemu behaviour was to truncate to 4 byte alignment, wh= ich + * is obviously wrong. The only place I can see this used is in t= he + * Linux kernel which begins with page alignment, advancing by 32, + * so is always aligned. Assume truncation as the simpler option. + * + * Since the loads and stores are paired, allow the copy to happen + * in the host endianness. The copy need not be atomic. + */ { + MemOp mop =3D MO_128 | MO_ATOM_IFALIGN_PAIR; TCGv saddr =3D tcg_temp_new(); TCGv daddr =3D tcg_temp_new(); - TCGv four =3D tcg_constant_tl(4); - TCGv_i32 tmp =3D tcg_temp_new_i32(); - int i; + TCGv_i128 tmp =3D tcg_temp_new_i128(); =20 - tcg_gen_andi_tl(saddr, src, -4); - tcg_gen_andi_tl(daddr, addr, -4); - for (i =3D 0; i < 32; i +=3D 4) { - /* Since the loads and stores are paired, allow the - copy to happen in the host endianness. */ - tcg_gen_qemu_ld_i32(tmp, saddr, da->mem_idx, MO_UL); - tcg_gen_qemu_st_i32(tmp, daddr, da->mem_idx, MO_UL); - tcg_gen_add_tl(saddr, saddr, four); - tcg_gen_add_tl(daddr, daddr, four); - } + tcg_gen_andi_tl(saddr, src, -32); + tcg_gen_andi_tl(daddr, addr, -32); + tcg_gen_qemu_ld_i128(tmp, saddr, da->mem_idx, mop); + tcg_gen_qemu_st_i128(tmp, daddr, da->mem_idx, mop); + tcg_gen_addi_tl(saddr, saddr, 16); + tcg_gen_addi_tl(daddr, daddr, 16); + tcg_gen_qemu_ld_i128(tmp, saddr, da->mem_idx, mop); + tcg_gen_qemu_st_i128(tmp, daddr, da->mem_idx, mop); } break; =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853550; cv=none; d=zohomail.com; s=zohoarc; b=ZOWP4HK7/YSvwgHDlQgEwNt7BYRQRLbOXThABwLTQFLkouOmlTC7vm0IDOYi9poPQZST7zOzdCaieMR5pjaDh6tUVztRR00gSGHeH6SsglHnSr++5175BxbvvzEWu6PElSebcc+VlkiTtTJrWI9LHbfPizzFSrdZ5zsyRsLqbnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853550; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wxeXPbX6hjz+X/sMPb06TGA1YfBXK5OBxElnE5+fhQk=; b=QU1oc3hb3U3MitMblVqd2RDue6aopzH/koP2SgBMMk5zoxiHUR1qu8lVKDHWulnNjc8jMyG49XVBuOQugnr+LYw89b4reEhhzofeeelv1sNYXkKwPRUUgrRmvMpFfQm9vo0qGaGW9zqfEsaMN8L8LIF9B9Ntzh8IIWHTZ10VfJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170685355076017.321925612179598; Thu, 1 Feb 2024 21:59:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmTT-0003Wt-11; Fri, 02 Feb 2024 00:52:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmTG-000389-Bv for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:52:14 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmT4-00028v-5S for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:52:10 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6de0ba30994so344593b3a.1 for ; Thu, 01 Feb 2024 21:52:01 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:52:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853121; x=1707457921; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wxeXPbX6hjz+X/sMPb06TGA1YfBXK5OBxElnE5+fhQk=; b=aTTRVFbtUh3abWgsKDMitp0GxcizuJ3r723wzdPOlQNPXkyTsy2QN0eBK7O9XF3tou H4++dgQDLZ2Yk5j8/z2+I0aSGjRBAugyPz9D3QeepnnXw6wQohQ3eGffautB65KXm0Gd RG6fValmWdFYP/wgxGLNNaYk19KZctv/atXAn102lBZV4CdQ9UrPEYDV4NUhNdkH7xc5 0vsRsuYsbQ9R0J8Fnw9Zb+GT/HcZ2LEGHMbTP69uNqz1ZKQg6Jmf8BYcIZkiTGn8g4Da mIT4ZXmeVNDIIOtwjyHlHUSruLVKRGnv/B7bYNa/kraAWX1bIwenD/ax6GymwOiVFcGA OSmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853121; x=1707457921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wxeXPbX6hjz+X/sMPb06TGA1YfBXK5OBxElnE5+fhQk=; b=iFtCvtLnK2J3ftFL9F400Goyg78CqhVnzjELs8inSbLK0x254FNpcjGgFWBxtdXha1 z2pf0WBiy+5IlJkol9E3Ssx+j69Acq6JPNe8VXRmRl9nv001LMb+pRaoeNAsfPwjYepY jHO/UXgx2fgHTNit5gueyFqHMeM3rwrCuaZtyStDmmcYj+wnX+NXZzrob1igWCr4cfB1 t5EcyvhfNb9QoJM9f23ksWCdarq29UUR33FS/ICzTi15tAWmPhhufEtMwXmo+rRG1wO7 dBcMzGAwIJnZwipLNlRnQeLA6rjRYqDbKXt0WHeK7C1LRqzTmG6ny8+QHOQW9uLk1+HW lUyg== X-Gm-Message-State: AOJu0YyA5WX+LrJoowOIdW2P4JBqJVI3Vl7qUYzewvpdmznniHQYpVlq lgOoUOArOnbLp8xGuEbAivX3k7xxXV2xB5f1i9iXwfzYWKBNecR0gwCTUJZAKBqXx4J2WlyQGlM pPTA= X-Google-Smtp-Source: AGHT+IEo3AxLlqY/rOQUXGn/vh1xXLquTT+qBhXvXMs839/3HUI8pICyiWIXLbF0zzVFRQvnnQFjqg== X-Received: by 2002:a05:6a00:3cc8:b0:6dd:c5c2:3536 with SMTP id ln8-20020a056a003cc800b006ddc5c23536mr2073286pfb.2.1706853120866; Thu, 01 Feb 2024 21:52:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 37/57] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL Date: Fri, 2 Feb 2024 15:50:16 +1000 Message-Id: <20240202055036.684176-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853551798100009 Content-Type: text/plain; charset="utf-8" Align the operation to the 32-byte cacheline. Use 2 i128 instead of 4 i64. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-3-richard.henderson@linaro.org> --- target/sparc/translate.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1082aabc14..3a59262c9a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2172,23 +2172,22 @@ static void gen_stda_asi(DisasContext *dc, DisasASI= *da, TCGv addr, int rd) =20 case GET_ASI_BFILL: assert(TARGET_LONG_BITS =3D=3D 32); - /* Store 32 bytes of T64 to ADDR. */ - /* ??? The original qemu code suggests 8-byte alignment, dropping - the low bits, but the only place I can see this used is in the - Linux kernel with 32 byte alignment, which would make more sense - as a cacheline-style operation. */ + /* + * Store 32 bytes of [rd:rd+1] to ADDR. + * See comments for GET_ASI_COPY above. + */ { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - TCGv d_addr =3D tcg_temp_new(); - TCGv eight =3D tcg_constant_tl(8); - int i; + MemOp mop =3D MO_TE | MO_128 | MO_ATOM_IFALIGN_PAIR; + TCGv_i64 t8 =3D tcg_temp_new_i64(); + TCGv_i128 t16 =3D tcg_temp_new_i128(); + TCGv daddr =3D tcg_temp_new(); =20 - tcg_gen_concat_tl_i64(t64, lo, hi); - tcg_gen_andi_tl(d_addr, addr, -8); - for (i =3D 0; i < 32; i +=3D 8) { - tcg_gen_qemu_st_i64(t64, d_addr, da->mem_idx, da->memop); - tcg_gen_add_tl(d_addr, d_addr, eight); - } + tcg_gen_concat_tl_i64(t8, lo, hi); + tcg_gen_concat_i64_i128(t16, t8, t8); + tcg_gen_andi_tl(daddr, addr, -32); + tcg_gen_qemu_st_i128(t16, daddr, da->mem_idx, mop); + tcg_gen_addi_tl(daddr, daddr, 16); + tcg_gen_qemu_st_i128(t16, daddr, da->mem_idx, mop); } break; =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853136; cv=none; d=zohomail.com; s=zohoarc; b=MdZwJI7xzJdnHyi0Km4RMI0rO1ghl3Mhxon2cIohFG180jD0bDe93PXJhkaZ8J7VxJ5DnI8CjKBrVw6LKQgjbKxWD4/yZuhKwiIQt0enIK2wI3x8nwE4JryrIvIJqp19PGvFEtRfeEgs0CEmPNKHoxk7hE3Mxjh3whzQvva5WYY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853136; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HYTSRpCGethKLnoY2fpF4KOBgpBDTTihXu+DADLRFZw=; b=HlMc3kvBA5WnQEEPnUbamjVHt8SOSQvKkwxBieOgh3N9Uoy4qiCaN0HCv6TXOmKa0ISr/iEcI/dpEaWv0kQuW4fNmzH2MCiUl0PuGzoguJHJCmeF/BszOziLC1Mhz9BTpujOuWC+tvPcqw+gOByCWe+bt+dKpDQI7X9+//miPoA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853136637652.3591508758892; Thu, 1 Feb 2024 21:52:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmTA-00034Z-TH; Fri, 02 Feb 2024 00:52:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmT7-00033T-QU for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:52:05 -0500 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmT6-00029R-CS for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:52:05 -0500 Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3bbb4806f67so1238114b6e.3 for ; Thu, 01 Feb 2024 21:52:03 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:52:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853123; x=1707457923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HYTSRpCGethKLnoY2fpF4KOBgpBDTTihXu+DADLRFZw=; b=SxbBIAnh+mEUJfXX2oqKYBbyLGbvAW+0NnQIVH9c3VpmCsvcov3R7SzXdDjB1B9kZI 19w2NzjMGcVknhgAyWTJnfHVt6q1eiAT5ds7LySd0unjZWX8MOhsnXT6M2XLexo2mUg+ L0Z+XzDx6PQpXRS716I0w5y7woHfowNl94B8SRmAfEEpD+1dQD6C1KlVrfik/dEKFlG5 A+i7dmqYd3yrcWZVb98CuiVn+fo35iiOieT7yVzlNXIVf1ehFsSHFV6oGcpGbrc9r5oe CnmpmtJt+JaWJz22RDHvrH1W11c6hPnY+MCwkEyPAKAWV8dtw++l2LM9HpL46NPBOuh2 11xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853123; x=1707457923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HYTSRpCGethKLnoY2fpF4KOBgpBDTTihXu+DADLRFZw=; b=d8VNViicoa+2O+Ch5IhACgueXmBlRVBsSadQxOS0RZlAk/Ihx8AO0ou0U2VZwMFNRV CCFjhvGYRfn5/k1+XDJc4/J1l4ss4TwwgUYpDRXwwVf4fxfweh3bbGiiHT6+9RVdNsEh /z6Z3/8C6KgB9koVxYq8nioUjqZvusv/qoPUwWCP9JN22WgekMbaHJvzAy3XI6COO2Y2 7zaSXRTuOj9DxTsu5Tn/GUvhWJdhdvBBlLqnDZm96ppVLyRyzgJnorJx2LJsDk5Kx+6J rwhc/IOsDx/uLwhldAFEdCQYgnu4Tc06cCBwo/6AyK2NlmxUHns0o9YEJtzOHPG45A5W dh8w== X-Gm-Message-State: AOJu0YwlUO/azNgNqLDT2G88Mak+KAY1Iu9SBo68Np+1y/sFW6Kk23Fj 76KDA4iR52aHSlvB3ooshr/YvWmWcTLEhZR3mrB2/MF5qkvJXC+FX6L+3HU6nyny7LziHxsiP4v +xi4= X-Google-Smtp-Source: AGHT+IHNLNOvT7g2SZcmtcnLr1nMOTxMbyrvCp1UgsHd1DFD2mecBtm35Bmq7TrYGzxKUmteoR764w== X-Received: by 2002:a05:6808:3089:b0:3bf:be81:923f with SMTP id bl9-20020a056808308900b003bfbe81923fmr1122993oib.24.1706853123218; Thu, 01 Feb 2024 21:52:03 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCW4syu0BZIlc+TjlkGmv7yZ5hSe9DZKQ16WLTrqXy1Nk4iXOJx97MF/uN8v52uJ2sb94CZoXXyvPpeMEGShj28XxTsm9wBdCQ+WTjLCug== From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 38/57] target/sparc: Remove gen_dest_fpr_F Date: Fri, 2 Feb 2024 15:50:17 +1000 Message-Id: <20240202055036.684176-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853138428100003 Replace with tcg_temp_new_i32. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-4-richard.henderson@linaro.org> --- target/sparc/translate.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3a59262c9a..6824b5d835 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -246,11 +246,6 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned= int dst, TCGv_i32 v) gen_update_fprs_dirty(dc, dst); } =20 -static TCGv_i32 gen_dest_fpr_F(DisasContext *dc) -{ - return tcg_temp_new_i32(); -} - static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) { src =3D DFPREG(src); @@ -1873,7 +1868,7 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, memop |=3D MO_ALIGN_4; switch (size) { case MO_32: - d32 =3D gen_dest_fpr_F(dc); + d32 =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(d32, addr, da->mem_idx, memop); gen_store_fpr_F(dc, rd, d32); break; @@ -1938,7 +1933,7 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, case MO_32: d64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); - d32 =3D gen_dest_fpr_F(dc); + d32 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(d32, d64); gen_store_fpr_F(dc, rd, d32); break; @@ -2228,7 +2223,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) =20 s1 =3D gen_load_fpr_F(dc, rs); s2 =3D gen_load_fpr_F(dc, rd); - dst =3D gen_dest_fpr_F(dc); + dst =3D tcg_temp_new_i32(); zero =3D tcg_constant_i32(0); =20 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); @@ -4497,7 +4492,7 @@ static bool do_fd(DisasContext *dc, arg_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_F(dc); + dst =3D tcg_temp_new_i32(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, src); gen_store_fpr_F(dc, a->rd, dst); @@ -4539,7 +4534,7 @@ static bool do_env_fd(DisasContext *dc, arg_r_r *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - dst =3D gen_dest_fpr_F(dc); + dst =3D tcg_temp_new_i32(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); @@ -4697,7 +4692,7 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, =20 gen_op_clear_ieee_excp_and_FTT(); gen_op_load_fpr_QT1(QFPREG(a->rs)); - dst =3D gen_dest_fpr_F(dc); + dst =3D tcg_temp_new_i32(); func(dst, tcg_env); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853384; cv=none; d=zohomail.com; s=zohoarc; b=Wzy+id1C8jWoODAsdGbHmTLUo1BqJBwlx18dWpypDKd6hzMXEcg2RmjUyHU14wF1flOY588vhpALUmN0m7s3HzUFKCakyrkwCt//paCvL5dR1KqHjd5dVpgNl25dxwYorO8DPG1/8lL5umto/kN1UGBj5OH67iqFSRblZPqOeWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853384; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wMA0Lk36Fd1VwYxsHHHznBGVGpg1MsjG0n+eTevqqnA=; b=itsOSoaPE8xcZq5np4tvx1mnuYEJdoQPyHqt0XC7yiWAg27FDNj6HnTRibz8YWSyC0txN+MHS1AyFFYFsh2C1oUGG5b1K0lf5RtPVBWPv9fBZ9aE5Q9G2sNe2AW8LnIEUoChpAdm0t7L3rmKb7Zhq74dHjlMMqd1e6oQAD/Fgkc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853384117989.2149197942814; Thu, 1 Feb 2024 21:56:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmW9-0005OY-Mq; Fri, 02 Feb 2024 00:55:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmW8-0005KQ-4m for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:55:12 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmW6-0002uz-8r for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:55:11 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1d7232dcb3eso13085405ad.2 for ; Thu, 01 Feb 2024 21:55:09 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id je5-20020a170903264500b001d8a80cbb15sm752059plb.238.2024.02.01.21.55.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:55:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853308; x=1707458108; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wMA0Lk36Fd1VwYxsHHHznBGVGpg1MsjG0n+eTevqqnA=; b=YTCcuM7X2MKgH3Ng0t1D5I9ijyRwlMKRbWljKgf0iXdqnVmb6TIBTH3ywx53JP88/3 Rxb6Bj2vfqSsChuNoLpRlpAMNopcGkLazUT94Q79HycJZ15DAA9g0NZqDhp+as8rAO7G rcOPb9GjuD5/L2oD9ZihzQ7IBQ7xFeWOOtMJA0pw4C9ZJ6t/EpU3vX0SP4C9NUwGoEzs 2TOjidnWt4AmjfixEF+rJCpaozJpDW3fuIdK7MeQV5kv/lqALQF57aP5BWm0vk6UfcC1 a0LWXppJVGSoBLpGNRlhUYKhY/PUtsvB0LgGqKlP87KlVcek8kHLOB2E53npNk+xnILc f6lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853308; x=1707458108; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wMA0Lk36Fd1VwYxsHHHznBGVGpg1MsjG0n+eTevqqnA=; b=c4XuEim1URdCoig8xBoxBbD4lnBFuannKtZc/ty4ORHmuNW24YfAdZJXOV95nmoyq5 ixMl/vfdGE3Otu+1meGBNZ64Yuipj2X4+80qmKqOP7YrCOCYA6VR7VWrN9ZjAouhDuZl ePzigWgi/gSQ8xR+V2rLjYXatFBUyDcVEEfW+iKqEcagK+QpBtArCzKTa7i2HpE3OW9Y wIT2dA82tpnVSX2ClV+EVG00GTiG3QXsm3Alcl+v9kwkRG5A2nxPjXg0DabHylCUp6Kw JGKJitZLTb/EhCDUilaAw5meCssnAxjiEZJNWkWwcA8TObdIJsEsIaO/j6EuuEHqwopq SGfQ== X-Gm-Message-State: AOJu0YxM2+rIPlXPPBr+IEorasQ7vpbk+yTmZDjmZvqw800542cLlzFa vvJN+4+maTwpQkp3RFmWbd5422n8Q3oObVb2Z7aguW6byhzNzx9nLIZ8m9IEzE8Ra2FfHRJTfpd s5GY= X-Google-Smtp-Source: AGHT+IHBuwnC+L6I4AjIhaK0dpXIlbk9usstKsQ90l8bk5cVVWZZ/giS5jkrehM29qNBpUcdHNRzwA== X-Received: by 2002:a17:902:d2c4:b0:1d9:fbe:466e with SMTP id n4-20020a170902d2c400b001d90fbe466emr1714804plc.66.1706853308630; Thu, 01 Feb 2024 21:55:08 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCXOK9uOC5dZiAh9TM7kvnRV54p6rFR1Fei+yyOYAnItVwRsEH6f78SP4nS2lMez4/FSSkKBC2lFw+5Y71WbY26H/QCYz78q0mD/pTMb7Q== From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 39/57] target/sparc: Introduce gen_{load,store}_fpr_Q Date: Fri, 2 Feb 2024 15:50:18 +1000 Message-Id: <20240202055036.684176-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853385408100013 Use them for trans_FMOVq. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-5-richard.henderson@linaro.org> --- target/sparc/translate.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6824b5d835..c68f6ca94e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -264,6 +264,22 @@ static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsig= ned int dst) return cpu_fpr[DFPREG(dst) / 2]; } =20 +static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src) +{ + TCGv_i128 ret =3D tcg_temp_new_i128(); + + src =3D QFPREG(src); + tcg_gen_concat_i64_i128(ret, cpu_fpr[src / 2 + 1], cpu_fpr[src / 2]); + return ret; +} + +static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, TCGv_i128 = v) +{ + dst =3D DFPREG(dst); + tcg_gen_extr_i128_i64(cpu_fpr[dst / 2 + 1], cpu_fpr[dst / 2], v); + gen_update_fprs_dirty(dc, dst); +} + static void gen_op_load_fpr_QT0(unsigned int src) { tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + @@ -4615,7 +4631,7 @@ TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox) =20 static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a) { - int rd, rs; + TCGv_i128 t; =20 if (!avail_64(dc)) { return false; @@ -4628,11 +4644,8 @@ static bool trans_FMOVq(DisasContext *dc, arg_FMOVq = *a) } =20 gen_op_clear_ieee_excp_and_FTT(); - rd =3D QFPREG(a->rd); - rs =3D QFPREG(a->rs); - tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); - tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); - gen_update_fprs_dirty(dc, rd); + t =3D gen_load_fpr_Q(dc, a->rs); + gen_store_fpr_Q(dc, a->rd, t); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853360; cv=none; d=zohomail.com; s=zohoarc; b=YSfhQB2vmVGclzEq8Oq4k2aPP5edvL0Z/2zzcLp2v7ivQHDp92LiSt9Dgsdorv21gJWSf1W6wp4OEuUzXYblhjXwZmVVoMfAbZ6dJl3uu6KYpPAl7lXsMnkO+Me32TFoIqwjajQ25TrhkmGHqaAP71x3uD/FwGNDjfo58L8Qn8E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853360; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8dGYAfcgax5YHIoo7vejf9aHAeaL4GPpSPEIsOOmIaA=; b=YTx3SNFiIUtL+gcokFeku+LHr7nq1uhaTX99dG19kGxBtyBEA/gRteF0bEn7uWDUNeV4mR8f67gLTAIJKkMDesn31JR4+uAcWcHNb73vPSmQQB6v2ck0KPmj7y71np02zgkpElt2Pk7JdlG+7An9immHgMNlzGGJ6U297YPkApc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853360769186.9896265697805; Thu, 1 Feb 2024 21:56:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmWC-0005Uo-JA; Fri, 02 Feb 2024 00:55:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmWA-0005QA-JN for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:55:14 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmW8-0002vw-Hl for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:55:14 -0500 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1d7232dcb3eso13085555ad.2 for ; Thu, 01 Feb 2024 21:55:12 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id je5-20020a170903264500b001d8a80cbb15sm752059plb.238.2024.02.01.21.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:55:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853311; x=1707458111; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8dGYAfcgax5YHIoo7vejf9aHAeaL4GPpSPEIsOOmIaA=; b=MewDmPFqnm2ato1vvV2kTbptlWTZgXvbyPP/1H1C+fYNQJtDuJWp3yEUXTbUDHdVUd qotqdoPGOpt22fKxMYtGlCTlidmFZNeqIx5XvBFS0u94YjgmbCRUtcWwznjPsnNnG9NQ VeHw6zw6n3tgLYHtGdfoG3K4iR1RZLfOkqs8yHI8SOBvzS32V3nnxqnHitxlDttHBAOF /nz4IAiWvrntT7rxTjL9Tn5sGqpe/VvK5uvL08o1lqJFrT0bIz+1Xejzf7VLi7S0GEgH 4reNQdjWjlqnli3sJRGC/ENLOCiTZxOnaW99+/pkjAAdb26nGg4LeuWQg0FeFx/RQYd8 0S9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853311; x=1707458111; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8dGYAfcgax5YHIoo7vejf9aHAeaL4GPpSPEIsOOmIaA=; b=jPNJnsGBTYUIPs+c9ZBOQYK8mu/9rlGnogLUwtKAOVoW2uax0ZNzUc/WI4WV+owf+2 usXMZdxbX/C8ULUinJD6Fxmxgj4/ibCW8iclAa05HBXwLAxEwaw0LeVlo0TSki1RFXMp P+rhVK8+TUZPHd673L7LQbCgqokvePJIQumowbt/dT9E74ACfqWZWsvPlwOH7Ui566Ff Bmex+WCqr6XUt51L3URbujMOCg26coWQMErpYLM2icZD8MFl8+9sunuuobE+9mvtH3Jd fD5gETovK74gilgOTDq1fD82C427VjJYWG0dupifP2Q5tj6SmMCPhiCUAs5f0/qBj+Pn u9ew== X-Gm-Message-State: AOJu0Yx0DZXzJvCcqc7441OoSvNXotpZ9QgTfzlcXoBkJ6hX2EM/B4RO N386d1mLDAXcqEexLkYujd2qdanCL6s5RK2RRz0OKguI6IPhYzJ2EqaS22XPX0h6hUZG5y2r9cp zwx8= X-Google-Smtp-Source: AGHT+IGg+XJlNoTDtL+uAHM2Pe4MXto82urwX1XfIoFMCvY37gZCvC00kTJ3eTFHt0p74QkfH897TA== X-Received: by 2002:a17:902:da92:b0:1d8:b8df:79f4 with SMTP id j18-20020a170902da9200b001d8b8df79f4mr1583345plx.17.1706853310945; Thu, 01 Feb 2024 21:55:10 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCWqisI70b9F1SBz7BHTOES1wpvPw71wuSV7Yht4inVNacsG+Bz00ZTMrhoUkZpYlpzVkXOrgHTOes7q7ixExqGpurK6KTI70kbN048mKw== From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 40/57] target/sparc: Inline FNEG, FABS Date: Fri, 2 Feb 2024 15:50:19 +1000 Message-Id: <20240202055036.684176-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853361347100003 These are simple bit manipulation insns. Begin using i128 for float128. Implement FMOVq with do_qq. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org> --- target/sparc/helper.h | 6 ---- target/sparc/fop_helper.c | 34 --------------------- target/sparc/translate.c | 62 +++++++++++++++++++-------------------- 3 files changed, 30 insertions(+), 72 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 55eff66283..74a1575d21 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -37,7 +37,6 @@ DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl,= i64, int, i32) #endif DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) -DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f32) @@ -48,7 +47,6 @@ DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64) DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32) @@ -61,7 +59,6 @@ DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env, = f32, f32) DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_1(fabsq, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env) @@ -90,15 +87,12 @@ DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f3= 2, f32) DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32) DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64) =20 -DEF_HELPER_FLAGS_1(fnegs, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32) DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, void, env, s32) =20 DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32) =20 #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_1(fnegd, TCG_CALL_NO_RWG_SE, f64, f64) -DEF_HELPER_FLAGS_1(fnegq, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64) DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64) DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 0f8aa3abcd..d6fb769769 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -114,23 +114,6 @@ void helper_fdmulq(CPUSPARCState *env, float64 src1, f= loat64 src2) &env->fp_status); } =20 -float32 helper_fnegs(float32 src) -{ - return float32_chs(src); -} - -#ifdef TARGET_SPARC64 -float64 helper_fnegd(float64 src) -{ - return float64_chs(src); -} - -F_HELPER(neg, q) -{ - QT0 =3D float128_chs(QT1); -} -#endif - /* Integer to float conversion. */ float32 helper_fitos(CPUSPARCState *env, int32_t src) { @@ -229,23 +212,6 @@ int64_t helper_fqtox(CPUSPARCState *env) } #endif =20 -float32 helper_fabss(float32 src) -{ - return float32_abs(src); -} - -#ifdef TARGET_SPARC64 -float64 helper_fabsd(float64 src) -{ - return float64_abs(src); -} - -void helper_fabsq(CPUSPARCState *env) -{ - QT0 =3D float128_abs(QT1); -} -#endif - float32 helper_fsqrts(CPUSPARCState *env, float32 src) { return float32_sqrt(src, &env->fp_status); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c68f6ca94e..41952281dc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -43,9 +43,7 @@ #else # define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_done(E) qemu_build_not_reached() -# define gen_helper_fabsd(D, S) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() -# define gen_helper_fnegd(D, S) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached() @@ -61,7 +59,6 @@ # define gen_helper_write_softint(E, S) qemu_build_not_reached() # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() -# define gen_helper_fabsq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL= ; }) @@ -79,7 +76,6 @@ # define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL= ; }) -# define gen_helper_fnegq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fqtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fstox ({ qemu_build_not_reached(); NULL= ; }) @@ -1239,13 +1235,13 @@ static void gen_op_fmovs(TCGv_i32 dst, TCGv_i32 src) static void gen_op_fnegs(TCGv_i32 dst, TCGv_i32 src) { gen_op_clear_ieee_excp_and_FTT(); - gen_helper_fnegs(dst, src); + tcg_gen_xori_i32(dst, src, 1u << 31); } =20 static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src) { gen_op_clear_ieee_excp_and_FTT(); - gen_helper_fabss(dst, src); + tcg_gen_andi_i32(dst, src, ~(1u << 31)); } =20 static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src) @@ -1257,13 +1253,33 @@ static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src) static void gen_op_fnegd(TCGv_i64 dst, TCGv_i64 src) { gen_op_clear_ieee_excp_and_FTT(); - gen_helper_fnegd(dst, src); + tcg_gen_xori_i64(dst, src, 1ull << 63); } =20 static void gen_op_fabsd(TCGv_i64 dst, TCGv_i64 src) { gen_op_clear_ieee_excp_and_FTT(); - gen_helper_fabsd(dst, src); + tcg_gen_andi_i64(dst, src, ~(1ull << 63)); +} + +static void gen_op_fnegq(TCGv_i128 dst, TCGv_i128 src) +{ + TCGv_i64 l =3D tcg_temp_new_i64(); + TCGv_i64 h =3D tcg_temp_new_i64(); + + tcg_gen_extr_i128_i64(l, h, src); + tcg_gen_xori_i64(h, h, 1ull << 63); + tcg_gen_concat_i64_i128(dst, l, h); +} + +static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 src) +{ + TCGv_i64 l =3D tcg_temp_new_i64(); + TCGv_i64 h =3D tcg_temp_new_i64(); + + tcg_gen_extr_i128_i64(l, h, src); + tcg_gen_andi_i64(h, h, ~(1ull << 63)); + tcg_gen_concat_i64_i128(dst, l, h); } =20 #ifdef TARGET_SPARC64 @@ -4629,13 +4645,11 @@ TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod) TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod) TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox) =20 -static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a) +static bool do_qq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i128, TCGv_i128)) { TCGv_i128 t; =20 - if (!avail_64(dc)) { - return false; - } if (gen_trap_ifnofpu(dc)) { return true; } @@ -4645,30 +4659,14 @@ static bool trans_FMOVq(DisasContext *dc, arg_FMOVq= *a) =20 gen_op_clear_ieee_excp_and_FTT(); t =3D gen_load_fpr_Q(dc, a->rs); + func(t, t); gen_store_fpr_Q(dc, a->rd, t); return advance_pc(dc); } =20 -static bool do_qq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_env)) -{ - if (gen_trap_ifnofpu(dc)) { - return true; - } - if (gen_trap_float128(dc)) { - return true; - } - - gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); - func(tcg_env); - gen_op_store_QT0_fpr(QFPREG(a->rd)); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853529748100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-7-richard.henderson@linaro.org> --- target/sparc/helper.h | 2 +- target/sparc/fop_helper.c | 26 ++++++++++++++++++++++++-- target/sparc/translate.c | 12 +++++++----- 3 files changed, 32 insertions(+), 8 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 74a1575d21..eea2fa570c 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -43,7 +43,7 @@ DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f= 32) DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_RWG, i128, env, i128) DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env) #ifdef TARGET_SPARC64 diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index d6fb769769..d639e50965 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -26,6 +26,28 @@ #define QT0 (env->qt0) #define QT1 (env->qt1) =20 +static inline float128 f128_in(Int128 i) +{ + union { + Int128 i; + float128 f; + } u; + + u.i =3D i; + return u.f; +} + +static inline Int128 f128_ret(float128 f) +{ + union { + Int128 i; + float128 f; + } u; + + u.f =3D f; + return u.i; +} + static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t= ra) { target_ulong status =3D get_float_exception_flags(&env->fp_status); @@ -222,9 +244,9 @@ float64 helper_fsqrtd(CPUSPARCState *env, float64 src) return float64_sqrt(src, &env->fp_status); } =20 -void helper_fsqrtq(CPUSPARCState *env) +Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) { - QT0 =3D float128_sqrt(QT1, &env->fp_status); + return f128_ret(float128_sqrt(f128_in(src), &env->fp_status)); } =20 #define GEN_FCMP(name, size, reg1, reg2, FS, E) \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 41952281dc..ca98565c16 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4669,8 +4669,10 @@ TRANS(FNEGq, 64, do_qq, a, gen_op_fnegq) TRANS(FABSq, 64, do_qq, a, gen_op_fabsq) =20 static bool do_env_qq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_env)) + void (*func)(TCGv_i128, TCGv_env, TCGv_i128)) { + TCGv_i128 t; + if (gen_trap_ifnofpu(dc)) { return true; } @@ -4679,11 +4681,11 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); - func(tcg_env); + + t =3D gen_load_fpr_Q(dc, a->rs); + func(t, tcg_env, t); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); + gen_store_fpr_Q(dc, a->rd, t); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853411; cv=none; d=zohomail.com; s=zohoarc; b=KamJ57uuOLUQDelC0G/oNcjSik5DcuP+WEfM2w+MMJwCA1VkrtSb1I62Ou+CccSm1HHHAmOZ9kBDyyHa/SsOjCKkcuwkCCp1LsrkdmXcN9Qjn/TZrObJ0IbiCPjt4/+6hj5dlFzSgB1F1LAleQfvbAU7K117J69n5D4qG2kEtUI= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853413510100010 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-8-richard.henderson@linaro.org> --- target/sparc/helper.h | 12 +++++------- target/sparc/fop_helper.c | 29 ++++++++++++++--------------- target/sparc/translate.c | 13 +++++++------ 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index eea2fa570c..0a030fc908 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -67,17 +67,16 @@ DEF_HELPER_FLAGS_1(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env) #endif DEF_HELPER_2(raise_exception, noreturn, env, int) -#define F_HELPER_0_1(name) \ - DEF_HELPER_FLAGS_1(f ## name, TCG_CALL_NO_RWG, void, env) =20 DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_RWG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_RWG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_RWG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_RWG, f64, env, f64, f64) -F_HELPER_0_1(addq) -F_HELPER_0_1(subq) -F_HELPER_0_1(mulq) -F_HELPER_0_1(divq) + +DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_RWG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_RWG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fmulq, TCG_CALL_NO_RWG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fdivq, TCG_CALL_NO_RWG, i128, env, i128, i128) =20 DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_RWG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_RWG, f32, env, f32, f32) @@ -135,6 +134,5 @@ VIS_CMPHELPER(cmpeq) VIS_CMPHELPER(cmple) VIS_CMPHELPER(cmpne) #endif -#undef F_HELPER_0_1 #undef VIS_HELPER #undef VIS_CMPHELPER diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index d639e50965..ceb64d802f 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -98,22 +98,22 @@ target_ulong helper_check_ieee_exceptions(CPUSPARCState= *env) return do_check_ieee_exceptions(env, GETPC()); } =20 -#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env) - -#define F_BINOP(name) \ +#define F_BINOP(name) \ float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \ - float32 src2) \ - { \ - return float32_ ## name (src1, src2, &env->fp_status); \ - } \ + float32 src2) \ + { \ + return float32_ ## name (src1, src2, &env->fp_status); \ + } \ float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\ - float64 src2) \ - { \ - return float64_ ## name (src1, src2, &env->fp_status); \ - } \ - F_HELPER(name, q) \ - { \ - QT0 =3D float128_ ## name (QT0, QT1, &env->fp_status); \ + float64 src2) \ + { \ + return float64_ ## name (src1, src2, &env->fp_status); \ + } \ + Int128 helper_f ## name ## q(CPUSPARCState * env, Int128 src1, \ + Int128 src2) \ + { \ + return f128_ret(float128_ ## name (f128_in(src1), f128_in(src2), \ + &env->fp_status)); \ } =20 F_BINOP(add); @@ -168,7 +168,6 @@ void helper_fxtoq(CPUSPARCState *env, int64_t src) QT0 =3D int64_to_float128(src, &env->fp_status); } #endif -#undef F_HELPER =20 /* floating point conversion */ float32 helper_fdtos(CPUSPARCState *env, float64 src) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ca98565c16..96aa7ed235 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4976,8 +4976,10 @@ static bool do_dddd(DisasContext *dc, arg_r_r_r *a, TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) =20 static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, - void (*func)(TCGv_env)) + void (*func)(TCGv_i128, TCGv_env, TCGv_i128, TCGv_i= 128)) { + TCGv_i128 src1, src2; + if (gen_trap_ifnofpu(dc)) { return true; } @@ -4986,12 +4988,11 @@ static bool do_env_qqq(DisasContext *dc, arg_r_r_r = *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT0(QFPREG(a->rs1)); - gen_op_load_fpr_QT1(QFPREG(a->rs2)); - func(tcg_env); + src1 =3D gen_load_fpr_Q(dc, a->rs1); + src2 =3D gen_load_fpr_Q(dc, a->rs2); + func(src1, tcg_env, src1, src2); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853549795100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-9-richard.henderson@linaro.org> --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 7 ++++--- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 0a030fc908..e770107eb0 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -98,13 +98,13 @@ DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s= 64) #endif DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) -DEF_HELPER_FLAGS_1(fqtos, TCG_CALL_NO_RWG, f32, env) +DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32) DEF_HELPER_FLAGS_1(fqtod, TCG_CALL_NO_RWG, f64, env) DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) -DEF_HELPER_FLAGS_1(fqtoi, TCG_CALL_NO_RWG, s32, env) +DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i128) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32) DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index ceb64d802f..657a14575d 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -180,9 +180,9 @@ float64 helper_fstod(CPUSPARCState *env, float32 src) return float32_to_float64(src, &env->fp_status); } =20 -float32 helper_fqtos(CPUSPARCState *env) +float32 helper_fqtos(CPUSPARCState *env, Int128 src) { - return float128_to_float32(QT1, &env->fp_status); + return float128_to_float32(f128_in(src), &env->fp_status); } =20 void helper_fstoq(CPUSPARCState *env, float32 src) @@ -211,9 +211,9 @@ int32_t helper_fdtoi(CPUSPARCState *env, float64 src) return float64_to_int32_round_to_zero(src, &env->fp_status); } =20 -int32_t helper_fqtoi(CPUSPARCState *env) +int32_t helper_fqtoi(CPUSPARCState *env, Int128 src) { - return float128_to_int32_round_to_zero(QT1, &env->fp_status); + return float128_to_int32_round_to_zero(f128_in(src), &env->fp_status); } =20 #ifdef TARGET_SPARC64 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 96aa7ed235..f70efb29a1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4692,8 +4692,9 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq) =20 static bool do_env_fq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_i32, TCGv_env)) + void (*func)(TCGv_i32, TCGv_env, TCGv_i128)) { + TCGv_i128 src; TCGv_i32 dst; =20 if (gen_trap_ifnofpu(dc)) { @@ -4704,9 +4705,9 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); + src =3D gen_load_fpr_Q(dc, a->rs); dst =3D tcg_temp_new_i32(); - func(dst, tcg_env); + func(dst, tcg_env, src); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); return advance_pc(dc); --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853442; cv=none; d=zohomail.com; s=zohoarc; b=H/LmmazAezGfpymn5iOBrKCmaOxIbhhgVJq/rTuVh3BPcHq3EWz6gmtrmIPwfYDPvJ9FZV/Oof8qteLgw7fcu6xn57ZYHtQ2oi5ihke0w39bZmf825c1I+bzv+i2IUBBuHGnG2NliUL303UEP6P27M5NsNAvYMILUfqLxGcF5Gw= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853443611100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-10-richard.henderson@linaro.org> --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 7 ++++--- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index e770107eb0..4cb3451878 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -100,7 +100,7 @@ DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f6= 4) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32) -DEF_HELPER_FLAGS_1(fqtod, TCG_CALL_NO_RWG, f64, env) +DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_RWG, f64, env, i128) DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) @@ -108,7 +108,7 @@ DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i1= 28) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32) DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) -DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env) +DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_RWG, s64, env, i128) =20 DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 657a14575d..9f39b933e8 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -190,9 +190,9 @@ void helper_fstoq(CPUSPARCState *env, float32 src) QT0 =3D float32_to_float128(src, &env->fp_status); } =20 -float64 helper_fqtod(CPUSPARCState *env) +float64 helper_fqtod(CPUSPARCState *env, Int128 src) { - return float128_to_float64(QT1, &env->fp_status); + return float128_to_float64(f128_in(src), &env->fp_status); } =20 void helper_fdtoq(CPUSPARCState *env, float64 src) @@ -227,9 +227,9 @@ int64_t helper_fdtox(CPUSPARCState *env, float64 src) return float64_to_int64_round_to_zero(src, &env->fp_status); } =20 -int64_t helper_fqtox(CPUSPARCState *env) +int64_t helper_fqtox(CPUSPARCState *env, Int128 src) { - return float128_to_int64_round_to_zero(QT1, &env->fp_status); + return float128_to_int64_round_to_zero(f128_in(src), &env->fp_status); } #endif =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f70efb29a1..6f75f4d5d6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4717,8 +4717,9 @@ TRANS(FqTOs, ALL, do_env_fq, a, gen_helper_fqtos) TRANS(FqTOi, ALL, do_env_fq, a, gen_helper_fqtoi) =20 static bool do_env_dq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_i64, TCGv_env)) + void (*func)(TCGv_i64, TCGv_env, TCGv_i128)) { + TCGv_i128 src; TCGv_i64 dst; =20 if (gen_trap_ifnofpu(dc)) { @@ -4729,9 +4730,9 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, } =20 gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); + src =3D gen_load_fpr_Q(dc, a->rs); dst =3D gen_dest_fpr_D(dc, a->rd); - func(dst, tcg_env); + func(dst, tcg_env, src); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853521; cv=none; d=zohomail.com; s=zohoarc; b=E/Ag3Ffykcx1ChFaCrnHvvVxYqFjA8+xjHqdPHO7gU6WPXhMlnb/+NLw05AkC0r7eZt0S+oKTAiYler3Gpg1A0bmw50QOv1ATjJXziSeORTGokIYEZWrNouPkf3d2NY6rK5ftruFwAud05DeMHkr/xpzaOYv4ryLrTN0QAZ2EPQ= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853521704100013 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-11-richard.henderson@linaro.org> --- target/sparc/helper.h | 16 ++++++------ target/sparc/fop_helper.c | 23 +++++++++-------- target/sparc/translate.c | 54 +++++++++++++++------------------------ 3 files changed, 41 insertions(+), 52 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 4cb3451878..7caae9a441 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -44,8 +44,8 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f= 64) DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_RWG, i128, env, i128) -DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env) +DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, tl, env, i128, i128) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) @@ -59,12 +59,12 @@ DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env= , f32, f32) DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_1(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpeq_fcc1, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_1(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env) +DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env, i128, i128) #endif DEF_HELPER_2(raise_exception, noreturn, env, int) =20 diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 9f39b933e8..faf75e651f 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -248,9 +248,12 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) return f128_ret(float128_sqrt(f128_in(src), &env->fp_status)); } =20 -#define GEN_FCMP(name, size, reg1, reg2, FS, E) \ - target_ulong glue(helper_, name) (CPUSPARCState *env) \ +#define GEN_FCMP(name, size, FS, E) \ + target_ulong glue(helper_, name) (CPUSPARCState *env, \ + Int128 src1, Int128 src2) \ { \ + float128 reg1 =3D f128_in(src1); \ + float128 reg2 =3D f128_in(src2); \ FloatRelation ret; \ target_ulong fsr; \ if (E) { \ @@ -316,33 +319,33 @@ GEN_FCMP_T(fcmpd, float64, 0, 0); GEN_FCMP_T(fcmpes, float32, 0, 1); GEN_FCMP_T(fcmped, float64, 0, 1); =20 -GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); -GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); +GEN_FCMP(fcmpq, float128, 0, 0); +GEN_FCMP(fcmpeq, float128, 0, 1); =20 #ifdef TARGET_SPARC64 GEN_FCMP_T(fcmps_fcc1, float32, 22, 0); GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0); -GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); +GEN_FCMP(fcmpq_fcc1, float128, 22, 0); =20 GEN_FCMP_T(fcmps_fcc2, float32, 24, 0); GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0); -GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); +GEN_FCMP(fcmpq_fcc2, float128, 24, 0); =20 GEN_FCMP_T(fcmps_fcc3, float32, 26, 0); GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0); -GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); +GEN_FCMP(fcmpq_fcc3, float128, 26, 0); =20 GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1); GEN_FCMP_T(fcmped_fcc1, float64, 22, 1); -GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); +GEN_FCMP(fcmpeq_fcc1, float128, 22, 1); =20 GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1); GEN_FCMP_T(fcmped_fcc2, float64, 24, 1); -GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); +GEN_FCMP(fcmpeq_fcc2, float128, 24, 1); =20 GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1); GEN_FCMP_T(fcmped_fcc3, float64, 26, 1); -GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); +GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); #endif #undef GEN_FCMP_T #undef GEN_FCMP diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6f75f4d5d6..6c003eed7c 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -276,22 +276,6 @@ static void gen_store_fpr_Q(DisasContext *dc, unsigned= int dst, TCGv_i128 v) gen_update_fprs_dirty(dc, dst); } =20 -static void gen_op_load_fpr_QT0(unsigned int src) -{ - tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + - offsetof(CPU_QuadU, ll.upper)); - tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 0) + - offsetof(CPU_QuadU, ll.lower)); -} - -static void gen_op_load_fpr_QT1(unsigned int src) -{ - tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt1)= + - offsetof(CPU_QuadU, ll.upper)); - tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 1) + - offsetof(CPU_QuadU, ll.lower)); -} - static void gen_op_store_QT0_fpr(unsigned int dst) { tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + @@ -1319,20 +1303,20 @@ static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1,= TCGv_i64 r_rs2) } } =20 -static void gen_op_fcmpq(int fccno) +static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpq(cpu_fsr, tcg_env); + gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env); + gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env); + gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env); + gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); break; } } @@ -1373,20 +1357,20 @@ static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1= , TCGv_i64 r_rs2) } } =20 -static void gen_op_fcmpeq(int fccno) +static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpeq(cpu_fsr, tcg_env); + gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env); + gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env); + gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env); + gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); break; } } @@ -1403,9 +1387,9 @@ static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, T= CGv_i64 r_rs2) gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 -static void gen_op_fcmpq(int fccno) +static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { - gen_helper_fcmpq(cpu_fsr, tcg_env); + gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) @@ -1418,9 +1402,9 @@ static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, = TCGv_i64 r_rs2) gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 -static void gen_op_fcmpeq(int fccno) +static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { - gen_helper_fcmpeq(cpu_fsr, tcg_env); + gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); } #endif =20 @@ -5144,6 +5128,8 @@ TRANS(FCMPEd, ALL, do_fcmpd, a, true) =20 static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e) { + TCGv_i128 src1, src2; + if (avail_32(dc) && a->cc !=3D 0) { return false; } @@ -5155,12 +5141,12 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a= , bool e) } =20 gen_op_clear_ieee_excp_and_FTT(); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853545841100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-12-richard.henderson@linaro.org> --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 9 +++++---- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 7caae9a441..5e93342583 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -87,7 +87,7 @@ DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32= , f32) DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64) =20 DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32) -DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, void, env, s32) +DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, i128, env, s32) =20 DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32) =20 @@ -99,7 +99,7 @@ DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64) DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) -DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32) +DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, i128, env, f32) DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_RWG, f64, env, i128) DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index faf75e651f..c7dc835d28 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -147,9 +147,9 @@ float64 helper_fitod(CPUSPARCState *env, int32_t src) return int32_to_float64(src, &env->fp_status); } =20 -void helper_fitoq(CPUSPARCState *env, int32_t src) +Int128 helper_fitoq(CPUSPARCState *env, int32_t src) { - QT0 =3D int32_to_float128(src, &env->fp_status); + return f128_ret(int32_to_float128(src, &env->fp_status)); } =20 #ifdef TARGET_SPARC64 @@ -185,9 +185,9 @@ float32 helper_fqtos(CPUSPARCState *env, Int128 src) return float128_to_float32(f128_in(src), &env->fp_status); } =20 -void helper_fstoq(CPUSPARCState *env, float32 src) +Int128 helper_fstoq(CPUSPARCState *env, float32 src) { - QT0 =3D float32_to_float128(src, &env->fp_status); + return f128_ret(float32_to_float128(src, &env->fp_status)); } =20 float64 helper_fqtod(CPUSPARCState *env, Int128 src) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6c003eed7c..6522a9b0c8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4726,9 +4726,10 @@ TRANS(FqTOd, ALL, do_env_dq, a, gen_helper_fqtod) TRANS(FqTOx, 64, do_env_dq, a, gen_helper_fqtox) =20 static bool do_env_qf(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_env, TCGv_i32)) + void (*func)(TCGv_i128, TCGv_env, TCGv_i32)) { TCGv_i32 src; + TCGv_i128 dst; =20 if (gen_trap_ifnofpu(dc)) { return true; @@ -4739,9 +4740,9 @@ static bool do_env_qf(DisasContext *dc, arg_r_r *a, =20 gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_F(dc, a->rs); - func(tcg_env, src); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); + dst =3D tcg_temp_new_i128(); + func(dst, tcg_env, src); + gen_store_fpr_Q(dc, a->rd, dst); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853415; cv=none; d=zohomail.com; s=zohoarc; b=MYIpEDb67IRxxhkE+zDSc7HQQf8YyX/V6jjhXiqpYp4Ihlh4IETYh7dNiRQw5gxlPuBa9kkA8J3nOsz3JehiIXEzK43xeToWCMAe9BUfjYZSi+ia0OVGyDOBJ1vPL0HBuytGZwuM/oXuI8/FQE298IPKQRNl2h0vXg4Q91lVNAI= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853417477100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-13-richard.henderson@linaro.org> --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 9 +++++---- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 5e93342583..20f67f89b0 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -94,14 +94,14 @@ DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s3= 2) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64) DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64) -DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64) +DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, i128, env, s64) #endif DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, i128, env, f32) DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_RWG, f64, env, i128) -DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) +DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, i128, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i128) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index c7dc835d28..9a0110e201 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -163,9 +163,9 @@ float64 helper_fxtod(CPUSPARCState *env, int64_t src) return int64_to_float64(src, &env->fp_status); } =20 -void helper_fxtoq(CPUSPARCState *env, int64_t src) +Int128 helper_fxtoq(CPUSPARCState *env, int64_t src) { - QT0 =3D int64_to_float128(src, &env->fp_status); + return f128_ret(int64_to_float128(src, &env->fp_status)); } #endif =20 @@ -195,9 +195,9 @@ float64 helper_fqtod(CPUSPARCState *env, Int128 src) return float128_to_float64(f128_in(src), &env->fp_status); } =20 -void helper_fdtoq(CPUSPARCState *env, float64 src) +Int128 helper_fdtoq(CPUSPARCState *env, float64 src) { - QT0 =3D float64_to_float128(src, &env->fp_status); + return f128_ret(float64_to_float128(src, &env->fp_status)); } =20 /* Float to integer conversion. */ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6522a9b0c8..d478a2fcd0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4750,9 +4750,10 @@ TRANS(FiTOq, ALL, do_env_qf, a, gen_helper_fitoq) TRANS(FsTOq, ALL, do_env_qf, a, gen_helper_fstoq) =20 static bool do_env_qd(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_env, TCGv_i64)) + void (*func)(TCGv_i128, TCGv_env, TCGv_i64)) { TCGv_i64 src; + TCGv_i128 dst; =20 if (gen_trap_ifnofpu(dc)) { return true; @@ -4763,9 +4764,9 @@ static bool do_env_qd(DisasContext *dc, arg_r_r *a, =20 gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_D(dc, a->rs); - func(tcg_env, src); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); + dst =3D tcg_temp_new_i128(); + func(dst, tcg_env, src); + gen_store_fpr_Q(dc, a->rd, dst); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853518; cv=none; d=zohomail.com; s=zohoarc; b=ed1XgBmBEP4GBkOawbOyMyaCFa0si11A91/zYnQYRzLN0FBFtkcGElqTAVZwzJydvzpPqLfCNjmxY2V1oz0yCR5QRcV9MPxqIe5avhlNrOg7GFBTGg8sMaXdsmYNl5Xfmb33FRe3vRgcgINW0UbrLE+z9m+n9fA73sHlkvEOODo= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853519750100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-14-richard.henderson@linaro.org> --- target/sparc/helper.h | 2 +- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 15 ++++----------- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 20f67f89b0..f7aeb31169 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -84,7 +84,7 @@ DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_RWG, f32, env, f32,= f32) DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f32, f32) =20 DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32) -DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, i128, env, f64, f64) =20 DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32) DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, i128, env, s32) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 9a0110e201..cd9b212597 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -129,11 +129,11 @@ float64 helper_fsmuld(CPUSPARCState *env, float32 src= 1, float32 src2) &env->fp_status); } =20 -void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2) +Int128 helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2) { - QT0 =3D float128_mul(float64_to_float128(src1, &env->fp_status), - float64_to_float128(src2, &env->fp_status), - &env->fp_status); + return f128_ret(float128_mul(float64_to_float128(src1, &env->fp_status= ), + float64_to_float128(src2, &env->fp_status= ), + &env->fp_status)); } =20 /* Integer to float conversion. */ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d478a2fcd0..d12de5ae5c 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -276,14 +276,6 @@ static void gen_store_fpr_Q(DisasContext *dc, unsigned= int dst, TCGv_i128 v) gen_update_fprs_dirty(dc, dst); } =20 -static void gen_op_store_QT0_fpr(unsigned int dst) -{ - tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + - offsetof(CPU_QuadU, ll.upper)); - tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 0) + - offsetof(CPU_QuadU, ll.lower)); -} - /* moves */ #ifdef CONFIG_USER_ONLY #define supervisor(dc) 0 @@ -4992,6 +4984,7 @@ TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq) static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a) { TCGv_i64 src1, src2; + TCGv_i128 dst; =20 if (gen_trap_ifnofpu(dc)) { return true; @@ -5003,10 +4996,10 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_= r *a) gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); - gen_helper_fdmulq(tcg_env, src1, src2); + dst =3D tcg_temp_new_i128(); + gen_helper_fdmulq(dst, tcg_env, src1, src2); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - gen_op_store_QT0_fpr(QFPREG(a->rd)); - gen_update_fprs_dirty(dc, QFPREG(a->rd)); + gen_store_fpr_Q(dc, a->rd, dst); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id je5-20020a170903264500b001d8a80cbb15sm752059plb.238.2024.02.01.21.55.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:55:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853330; x=1707458130; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OishrheNzxUH4jK3pSUw3hY8ZUKqc85FNfgHLzLsYl4=; b=P4ozukAlmYLdMOPes77Ewylm0avBOR9eWTNgU1nFPt23BWiaWboXvJy1jFCYPdqWXR RRj6y1GUqbKaxggW63cbL4M+ikEMxjD/+KYEHiJn+dl01cIzcMSiYGaKy2je5jCvAolk Wo+1y2StXreW1U/gZ8jorFmvgtrx5dL9ImfqWKLjeojp6kxq6kx4bfxUOtObRvJzV179 NagP89RDnILbQDm1bvHnSO90WXlFbvSfHIGoCetx1UQQUi536ACkXzKqJQWtJvFB/H1Y Qr7Je70HY/w6m3Z73nND1zzh0QcKqVxJoJ7aXz4hxG1m3YqgmhYt+4JF+VQb5tqNnc3z /3vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853330; x=1707458130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OishrheNzxUH4jK3pSUw3hY8ZUKqc85FNfgHLzLsYl4=; b=Me9+OJL0bq1Sy4Nb6WmHX9J+cHG20ukSCFWGob9ITF5SfF2gjEdO2iYRiqmtsbh1gC hhHTU7JWuhP70oCfpBissGo9jmKte3gsrz9+ow0imBJWT0+1nzyMib1uzjzLcvQZyyh8 Ow8gxZ75pMxIsxl8nsSNNPihbLrglBkSDelN8Uu77gwxNFSrvvF0ShS7C3TmQLQh663x yZRCNHG72H5fucrE5roYkbR73qhb8D+zP4iMA+8aKhiPzMTF4Dxqz4NmaYf0OheKcZpW hI1VCWCUkxTPiU97qPDD3cXsTK2Nn85/dUGkhZvPOr74HOuCJKmrEVB1L7MDzqepVh5r 4UZA== X-Gm-Message-State: AOJu0YxDxFj96EFgJ6g7cT7ZYCwFZzRBqE7ZjwHVLRilamv0H2RreWnO U2VQVtaCg+nC83eUzfkI3/IFSJloB5ljTQxUZSA4O0h/K6+dpQE5/iXq+dOwYUiS4bpEiImmPsM DVl0= X-Google-Smtp-Source: AGHT+IE/nMmbl8LDWlJATjAVfRXSt5MM2ZeKcTPUNLXYukXCC8R6o7EKrCjZbijj1mhrrhNqbvaaWw== X-Received: by 2002:a17:902:e5d1:b0:1d9:2e9d:8cb6 with SMTP id u17-20020a170902e5d100b001d92e9d8cb6mr2004344plf.15.1706853330679; Thu, 01 Feb 2024 21:55:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 49/57] target/sparc: Remove qt0, qt1 temporaries Date: Fri, 2 Feb 2024 15:50:28 +1000 Message-Id: <20240202055036.684176-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853531847100007 Content-Type: text/plain; charset="utf-8" These are no longer used for passing data to/from helpers. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-15-richard.henderson@linaro.org> --- target/sparc/cpu.h | 2 -- target/sparc/fop_helper.c | 3 --- target/sparc/ldst_helper.c | 3 --- 3 files changed, 8 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 1e076f6355..75c46e2736 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -509,8 +509,6 @@ struct CPUArchState { uint64_t mmubpregs[4]; uint64_t prom_addr; #endif - /* temporary float registers */ - float128 qt0, qt1; float_status fp_status; #if defined(TARGET_SPARC64) #define MAXTL_MAX 8 diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index cd9b212597..7353a61237 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -23,9 +23,6 @@ #include "exec/helper-proto.h" #include "fpu/softfloat.h" =20 -#define QT0 (env->qt0) -#define QT1 (env->qt1) - static inline float128 f128_in(Int128 i) { union { diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 52aa6c631b..1ecd58e8ff 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -66,9 +66,6 @@ #endif #endif =20 -#define QT0 (env->qt0) -#define QT1 (env->qt1) - #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) /* Calculates TSB pointer value for fault page size * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853373; cv=none; d=zohomail.com; s=zohoarc; b=dsVd/VgBFhan/hXcj4M0NJtGoOreGnRtFdi3aaBMmEf2YF8cuBRlYRNZL2NuikFtJ2uC3Cvfo6TQtlD5q0spa/HECx04tgnGOWzd+FwPqsTrJ4McO3EAgYuasUgINzWEaCab6ny8jeQyuX4VICYwso0mKqYEKP3IBcM1zg773sw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853373; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+CKO74e1aAnMx7S2wTd4pu1cbyRnMGYoiupzj8eCl8M=; b=Tkt2KksC4PytfsNKX0UgF7qcol6GFH91tpkl8sU+IwnAOdaqoM4ZebLcN9b2RXK7FFR6ii0uYaEcxeQ5ZZHzZdPNGzKN6kR8eajm4GbbBgWMSrcnxcBHKX3SWhx1/VB+ZfqHytZiL5CX/oAiw4U+a2d0UEbyAUGaPoyZc31JeUc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853373189359.98050151211396; Thu, 1 Feb 2024 21:56:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmWY-0006ue-QR; Fri, 02 Feb 2024 00:55:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmWX-0006pr-63 for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:55:37 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmWU-000346-C9 for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:55:36 -0500 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1d7232dcb3eso13086815ad.2 for ; Thu, 01 Feb 2024 21:55:33 -0800 (PST) Received: from stoup.. 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AJvYcCUUULTXZhJPPiQ/NYBug4oGWMj6Lnlb6OLTjn2wwWQW77/HRYsNKOThL0A3Nf9qTvhq0ZAdm1B+qSZ3+mQCdlzEjxkPbGyRt3dJ42Ancg== From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 50/57] target/sparc: Introduce cpu_get_fsr, cpu_put_fsr Date: Fri, 2 Feb 2024 15:50:29 +1000 Message-Id: <20240202055036.684176-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853375233100003 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org> --- target/sparc/cpu.h | 4 +++- target/sparc/helper.h | 1 + linux-user/sparc/cpu_loop.c | 2 +- linux-user/sparc/signal.c | 14 +++++++++----- target/sparc/cpu.c | 5 +++-- target/sparc/fop_helper.c | 21 +++++++++++++++++++-- target/sparc/gdbstub.c | 8 ++++---- target/sparc/machine.c | 36 ++++++++++++++++++++++++++++++++++-- target/sparc/translate.c | 7 ++++++- 9 files changed, 80 insertions(+), 18 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 75c46e2736..3cf8cc2d0b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -617,7 +617,9 @@ void sparc_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data); =20 -/* cpu-exec.c */ +/* fop_helper.c */ +target_ulong cpu_get_fsr(CPUSPARCState *); +void cpu_put_fsr(CPUSPARCState *, target_ulong); =20 /* win_helper.c */ target_ulong cpu_get_psr(CPUSPARCState *env1); diff --git a/target/sparc/helper.h b/target/sparc/helper.h index f7aeb31169..cc8db50d75 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,6 +36,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, = int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) +DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 3c1bde00dd..50424a54df 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -293,7 +293,7 @@ void cpu_loop (CPUSPARCState *env) case TT_FP_EXCP: { int code =3D TARGET_FPE_FLTUNK; - target_ulong fsr =3D env->fsr; + target_ulong fsr =3D cpu_get_fsr(env); =20 if ((fsr & FSR_FTT_MASK) =3D=3D FSR_FTT_IEEE_EXCP) { if (fsr & FSR_NVC) { diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index dfcae707e0..c2dc1000e2 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -199,20 +199,21 @@ static void save_fpu(struct target_siginfo_fpu *fpu, = CPUSPARCState *env) for (i =3D 0; i < 32; ++i) { __put_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __put_user(env->fsr, &fpu->si_fsr); + __put_user(cpu_get_fsr(env), &fpu->si_fsr); __put_user(env->gsr, &fpu->si_gsr); __put_user(env->fprs, &fpu->si_fprs); #else for (i =3D 0; i < 16; ++i) { __put_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __put_user(env->fsr, &fpu->si_fsr); + __put_user(cpu_get_fsr(env), &fpu->si_fsr); __put_user(0, &fpu->si_fpqdepth); #endif } =20 static void restore_fpu(struct target_siginfo_fpu *fpu, CPUSPARCState *env) { + target_ulong fsr; int i; =20 #ifdef TARGET_SPARC64 @@ -230,15 +231,16 @@ static void restore_fpu(struct target_siginfo_fpu *fp= u, CPUSPARCState *env) __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } } - __get_user(env->fsr, &fpu->si_fsr); __get_user(env->gsr, &fpu->si_gsr); env->fprs |=3D fprs; #else for (i =3D 0; i < 16; ++i) { __get_user(env->fpr[i].ll, &fpu->si_double_regs[i]); } - __get_user(env->fsr, &fpu->si_fsr); #endif + + __get_user(fsr, &fpu->si_fsr); + cpu_put_fsr(env, fsr); } =20 #ifdef TARGET_ARCH_HAS_SETUP_FRAME @@ -662,6 +664,7 @@ void sparc64_set_context(CPUSPARCState *env) __get_user(fenab, &(fpup->mcfpu_enab)); if (fenab) { abi_ulong fprs; + abi_ulong fsr; =20 /* * We use the FPRS from the guest only in deciding whether @@ -690,7 +693,8 @@ void sparc64_set_context(CPUSPARCState *env) __get_user(env->fpr[i].ll, &(fpup->mcfpu_fregs.dregs[i])); } } - __get_user(env->fsr, &(fpup->mcfpu_fsr)); + __get_user(fsr, &(fpup->mcfpu_fsr)); + cpu_put_fsr(env, fsr); __get_user(env->gsr, &(fpup->mcfpu_gsr)); } unlock_user_struct(ucp, ucp_addr, 0); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index afa62723fe..1897ab230d 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -670,7 +670,7 @@ static void sparc_cpu_dump_state(CPUState *cs, FILE *f,= int flags) env->cansave, env->canrestore, env->otherwin, env->wstate, env->cleanwin, env->nwindows - 1 - env->cwp); qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %01= 6x\n", - env->fsr, env->y, env->fprs); + cpu_get_fsr(env), env->y, env->fprs); =20 #else qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); @@ -679,7 +679,7 @@ static void sparc_cpu_dump_state(CPUState *cs, FILE *f,= int flags) env->psrps ? 'P' : '-', env->psret ? 'E' : '-', env->wim); qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", - env->fsr, env->y); + cpu_get_fsr(env), env->y); #endif qemu_fprintf(f, "\n"); } @@ -798,6 +798,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) env->version |=3D env->def.maxtl << 8; env->version |=3D env->def.nwindows - 1; #endif + cpu_put_fsr(env, 0); =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 7353a61237..70b38011d2 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -347,10 +347,22 @@ GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); #undef GEN_FCMP_T #undef GEN_FCMP =20 -static void set_fsr(CPUSPARCState *env, target_ulong fsr) +target_ulong cpu_get_fsr(CPUSPARCState *env) +{ + return env->fsr; +} + +target_ulong helper_get_fsr(CPUSPARCState *env) +{ + return cpu_get_fsr(env); +} + +static void set_fsr_nonsplit(CPUSPARCState *env, target_ulong fsr) { int rnd_mode; =20 + env->fsr =3D fsr; + switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: rnd_mode =3D float_round_nearest_even; @@ -369,7 +381,12 @@ static void set_fsr(CPUSPARCState *env, target_ulong f= sr) set_float_rounding_mode(rnd_mode, &env->fp_status); } =20 +void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) +{ + set_fsr_nonsplit(env, fsr); +} + void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) { - set_fsr(env, fsr); + set_fsr_nonsplit(env, fsr); } diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index a1c8fdc4d5..d1586b2392 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -64,7 +64,7 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) case 69: return gdb_get_rega(mem_buf, env->npc); case 70: - return gdb_get_rega(mem_buf, env->fsr); + return gdb_get_rega(mem_buf, cpu_get_fsr(env)); case 71: return gdb_get_rega(mem_buf, 0); /* csr */ default: @@ -94,7 +94,7 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) ((env->pstate & 0xfff) << 8) | cpu_get_cwp64(env)); case 83: - return gdb_get_regl(mem_buf, env->fsr); + return gdb_get_regl(mem_buf, cpu_get_fsr(env)); case 84: return gdb_get_regl(mem_buf, env->fprs); case 85: @@ -156,7 +156,7 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) env->npc =3D tmp; break; case 70: - env->fsr =3D tmp; + cpu_put_fsr(env, tmp); break; default: return 0; @@ -191,7 +191,7 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) cpu_put_cwp64(env, tmp & 0xff); break; case 83: - env->fsr =3D tmp; + cpu_put_fsr(env, tmp); break; case 84: env->fprs =3D tmp; diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 2b5686c330..48e0cf22f3 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -83,6 +83,32 @@ static const VMStateInfo vmstate_psr =3D { .put =3D put_psr, }; =20 +static int get_fsr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + SPARCCPU *cpu =3D opaque; + target_ulong val =3D qemu_get_betl(f); + + cpu_put_fsr(&cpu->env, val); + return 0; +} + +static int put_fsr(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + SPARCCPU *cpu =3D opaque; + target_ulong val =3D cpu_get_fsr(&cpu->env); + + qemu_put_betl(f, val); + return 0; +} + +static const VMStateInfo vmstate_fsr =3D { + .name =3D "fsr", + .get =3D get_fsr, + .put =3D put_fsr, +}; + #ifdef TARGET_SPARC64 static int get_xcc(QEMUFile *f, void *opaque, size_t size, const VMStateField *field) @@ -157,7 +183,6 @@ const VMStateDescription vmstate_sparc_cpu =3D { VMSTATE_UINTTL(env.npc, SPARCCPU), VMSTATE_UINTTL(env.y, SPARCCPU), { - .name =3D "psr", .version_id =3D 0, .size =3D sizeof(uint32_t), @@ -165,7 +190,14 @@ const VMStateDescription vmstate_sparc_cpu =3D { .flags =3D VMS_SINGLE, .offset =3D 0, }, - VMSTATE_UINTTL(env.fsr, SPARCCPU), + { + .name =3D "fsr", + .version_id =3D 0, + .size =3D sizeof(target_ulong), + .info =3D &vmstate_fsr, + .flags =3D VMS_SINGLE, + .offset =3D 0, + }, VMSTATE_UINTTL(env.tbr, SPARCCPU), VMSTATE_INT32(env.interrupt_index, SPARCCPU), VMSTATE_UINT32(env.pil_in, SPARCCPU), diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d12de5ae5c..da4f167fa6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4417,13 +4417,18 @@ TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_= MASK, FSR_LDXFSR_OLDMASK) static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) { TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); 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It is easier to store it separately and merge it only upon read. While we're at it, use FSR_VER_SHIFT to initialize fpu_version. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-17-richard.henderson@linaro.org> --- target/sparc/cpu.h | 3 +++ target/sparc/cpu.c | 27 +++++++++++++-------------- target/sparc/fop_helper.c | 9 +++++++-- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 3cf8cc2d0b..216155d231 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -191,6 +191,9 @@ enum { #define FSR_NXC (1ULL << 0) #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) =20 +#define FSR_VER_SHIFT 17 +#define FSR_VER_MASK (7 << FSR_VER_SHIFT) + #define FSR_FTT2 (1ULL << 16) #define FSR_FTT1 (1ULL << 15) #define FSR_FTT0 (1ULL << 14) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1897ab230d..313ebc4c11 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -368,7 +368,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "Fujitsu MB86904", .iu_version =3D 0x04 << 24, /* Impl 0, ver 4 */ - .fpu_version =3D 4 << 17, /* FPU version 4 (Meiko) */ + .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0x04 << 24, /* Impl 0, ver 4 */ .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x00ffffc0, @@ -381,7 +381,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "Fujitsu MB86907", .iu_version =3D 0x05 << 24, /* Impl 0, ver 5 */ - .fpu_version =3D 4 << 17, /* FPU version 4 (Meiko) */ + .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0x05 << 24, /* Impl 0, ver 5 */ .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -394,7 +394,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI MicroSparc I", .iu_version =3D 0x41000000, - .fpu_version =3D 4 << 17, + .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x41000000, .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x007ffff0, @@ -407,7 +407,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI MicroSparc II", .iu_version =3D 0x42000000, - .fpu_version =3D 4 << 17, + .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x02000000, .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x00ffffc0, @@ -420,7 +420,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI MicroSparc IIep", .iu_version =3D 0x42000000, - .fpu_version =3D 4 << 17, + .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x04000000, .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x00ffffc0, @@ -433,7 +433,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 40", /* STP1020NPGA */ .iu_version =3D 0x41000000, /* SuperSPARC 2.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x00000800, /* SuperSPARC 2.x, no MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -446,7 +446,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 50", /* STP1020PGA */ .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000800, /* SuperSPARC 3.x, no MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -459,7 +459,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 51", .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000000, /* SuperSPARC 3.x, MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -473,7 +473,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 60", /* STP1020APGA */ .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000800, /* SuperSPARC 3.x, no MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -486,7 +486,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc 61", .iu_version =3D 0x44000000, /* SuperSPARC 3.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000000, /* SuperSPARC 3.x, MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -500,7 +500,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "TI SuperSparc II", .iu_version =3D 0x40000000, /* SuperSPARC II 1.x */ - .fpu_version =3D 0 << 17, + .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x08000000, /* SuperSPARC II 1.x, MXCC */ .mmu_bm =3D 0x00002000, .mmu_ctpr_mask =3D 0xffffffc0, @@ -514,7 +514,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "LEON2", .iu_version =3D 0xf2000000, - .fpu_version =3D 4 << 17, /* FPU version 4 (Meiko) */ + .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0xf2000000, .mmu_bm =3D 0x00004000, .mmu_ctpr_mask =3D 0x007ffff0, @@ -527,7 +527,7 @@ static const sparc_def_t sparc_defs[] =3D { { .name =3D "LEON3", .iu_version =3D 0xf3000000, - .fpu_version =3D 4 << 17, /* FPU version 4 (Meiko) */ + .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0xf3000000, .mmu_bm =3D 0x00000000, .mmu_ctpr_mask =3D 0xfffffffc, @@ -786,7 +786,6 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) #endif =20 env->version =3D env->def.iu_version; - env->fsr =3D env->def.fpu_version; env->nwindows =3D env->def.nwindows; #if !defined(TARGET_SPARC64) env->mmuregs[0] |=3D env->def.mmu_version; diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 70b38011d2..22b412adb5 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -349,7 +349,12 @@ GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); =20 target_ulong cpu_get_fsr(CPUSPARCState *env) { - return env->fsr; + target_ulong fsr =3D env->fsr; + + /* VER is kept completely separate until re-assembly. */ + fsr |=3D env->def.fpu_version; + + return fsr; } =20 target_ulong helper_get_fsr(CPUSPARCState *env) @@ -361,7 +366,7 @@ static void set_fsr_nonsplit(CPUSPARCState *env, target= _ulong fsr) { int rnd_mode; =20 - env->fsr =3D fsr; + env->fsr =3D fsr & ~FSR_VER_MASK; =20 switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853378; cv=none; d=zohomail.com; s=zohoarc; b=VQfQTp92oihUfEb3nn3MKvNA/XMMT7+9OTPZDmMZTBgdBEAfEvQ6UeP/qwv9mv1FzPcF6J+FVy0uZY/KJKb7EDH3HNy+aoQylqNq5BBNkN4XelhxwfqW67v38T27yVeXJeYBFRMZo6/P8fCkqEBpREHJ8bZVqV2x6h9PgQB5VPU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853378; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xswm8Y4EVntAPydwJ8PJUaf0qkJ0h3e6mOU1vrp0dGE=; b=DErHx91ZnMyyVtY8eaFrMAAh6J1jpAjXcOiai1ikNV6GOxtAuDb9hTq2TgBh41xuhDaJDkqTxP8rJY99Zryhqy5AroyDtxfpsPyDHCePpPU9Ns+pIFTeNCrPvu8ZlyzR9ZF+RQBFdUyVw5+N0uo/xiuPvHhs+arJb4h0+38fZro= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17068533786531018.6892024013035; Thu, 1 Feb 2024 21:56:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmWb-00073U-HR; Fri, 02 Feb 2024 00:55:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmWa-00071Z-Hn for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:55:40 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmWY-00039V-UX for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:55:40 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1d9607f2b3aso3073395ad.0 for ; Thu, 01 Feb 2024 21:55:38 -0800 (PST) Received: from stoup.. ([103.210.27.218]) by smtp.gmail.com with ESMTPSA id je5-20020a170903264500b001d8a80cbb15sm752059plb.238.2024.02.01.21.55.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:55:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853337; x=1707458137; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xswm8Y4EVntAPydwJ8PJUaf0qkJ0h3e6mOU1vrp0dGE=; b=w5AMC/ZOg5b62eUEol6KHNgHQNHD1NyRUNVwhecLG+AtKsqkmBGjgrZcbmhiOZ534G +TdhdERVbNoM4Su/rOdw8CqJGraU8BEymHZmEOQRS+5z5UjZNhXDdC98CTbDBeQr9TVm Oh+nbRV3FMqxiEVrfQB1cTptquldnlsYKTnJ0VMlWbjOXykY9dhJsllClC8fe3Ro5laT R+7OaMZqngcflm6hsYEi8U4Cw5AzS5I+VB21HqB0wc7Al7OZfme8DcERQuJcp1SviqN+ 1AaldRQ9d7/6Mk2jf6vlhgOvQGurPr9nwv7WnjqXTx+0mu8GJCg17XxOWQ6bBnTSzs7k PmpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853337; x=1707458137; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xswm8Y4EVntAPydwJ8PJUaf0qkJ0h3e6mOU1vrp0dGE=; b=CBPR3oDUHjYGsUgwTV8tRqKTy+X9R3I+ADgviWsGKyn4YJ/hZhosPSCHMbZlCynQ2G l7/TMnhgGWrbW7F0q7g0pJjQYHefkMgITamn04wiUpGBcXLQTDqEKokKaiNwHpENrH0d 2ECvlj7NqkKtDiyXgoNQaqHGkfJYRAzny1dnefE5y5Ljl2hxQgWh+LWWJ6LuBp4yWD8Y 7cK+Ir6aiI5dIJK0AhF39MAnpNVr756DpMrdmQK3j824+hoB7RZBPMqbvJzZyMf7uvYb hc+UthjlQMkknzTkQpC08qQp7rHsz38OuBVj5zeLgNUxocmazThCv8r2mS/EQricnUSk uh+w== X-Gm-Message-State: AOJu0Yw5Alh6pv1WzMgGZRmWLdtVQl+Y1N1athYaaL65KlFx8OqJ9UCZ GjknJVXJFeJqsrv0owGgnEBS2FfbCCFgzt4wfPSl/DgghV3T+RWmb3+lm0BUdBt1737Qd2IxROp eCSI= X-Google-Smtp-Source: AGHT+IFWaA1tkgiiwjpkrvC5aXlOkD8ksLnbC5TFsGreY06/8Gg9EyEeO36++IEhFOG84C/TqFKBzA== X-Received: by 2002:a17:903:32c5:b0:1d7:19ec:2eaf with SMTP id i5-20020a17090332c500b001d719ec2eafmr1943574plr.6.1706853337693; Thu, 01 Feb 2024 21:55:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 52/57] target/sparc: Clear cexc and ftt in do_check_ieee_exceptions Date: Fri, 2 Feb 2024 15:50:31 +1000 Message-Id: <20240202055036.684176-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853379337100001 Content-Type: text/plain; charset="utf-8" Don't do the clearing explicitly before each FPop, rather do it as part of the rest of exception handling. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-18-richard.henderson@linaro.org> --- target/sparc/fop_helper.c | 2 ++ target/sparc/translate.c | 16 ---------------- 2 files changed, 2 insertions(+), 16 deletions(-) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 22b412adb5..64f20e78f1 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -50,6 +50,8 @@ static target_ulong do_check_ieee_exceptions(CPUSPARCStat= e *env, uintptr_t ra) target_ulong status =3D get_float_exception_flags(&env->fp_status); target_ulong fsr =3D env->fsr; =20 + fsr &=3D FSR_FTT_CEXC_NMASK; + if (unlikely(status)) { /* Keep exception flags clear for next time. */ set_float_exception_flags(0, &env->fp_status); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index da4f167fa6..67bac6f65f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4524,7 +4524,6 @@ static bool do_env_ff(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); tmp =3D gen_load_fpr_F(dc, a->rs); func(tmp, tcg_env, tmp); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); @@ -4546,7 +4545,6 @@ static bool do_env_fd(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D tcg_temp_new_i32(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); @@ -4590,7 +4588,6 @@ static bool do_env_dd(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D gen_dest_fpr_D(dc, a->rd); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); @@ -4613,7 +4610,6 @@ static bool do_env_df(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D gen_dest_fpr_D(dc, a->rd); src =3D gen_load_fpr_F(dc, a->rs); func(dst, tcg_env, src); @@ -4661,8 +4657,6 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); - t =3D gen_load_fpr_Q(dc, a->rs); func(t, tcg_env, t); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); @@ -4685,7 +4679,6 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_Q(dc, a->rs); dst =3D tcg_temp_new_i32(); func(dst, tcg_env, src); @@ -4710,7 +4703,6 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_Q(dc, a->rs); dst =3D gen_dest_fpr_D(dc, a->rd); func(dst, tcg_env, src); @@ -4808,7 +4800,6 @@ static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); func(src1, tcg_env, src1, src2); @@ -4903,7 +4894,6 @@ static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D gen_dest_fpr_D(dc, a->rd); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); @@ -4930,7 +4920,6 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r = *a) return raise_unimpfpop(dc); } =20 - gen_op_clear_ieee_excp_and_FTT(); dst =3D gen_dest_fpr_D(dc, a->rd); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); @@ -4972,7 +4961,6 @@ static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_Q(dc, a->rs1); src2 =3D gen_load_fpr_Q(dc, a->rs2); func(src1, tcg_env, src1, src2); @@ -4998,7 +4986,6 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r = *a) return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); dst =3D tcg_temp_new_i128(); @@ -5087,7 +5074,6 @@ static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, = bool e) return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); if (e) { @@ -5112,7 +5098,6 @@ static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, = bool e) return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src1 =3D gen_load_fpr_D(dc, a->rs1); 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The current implementation is incorrect, in that double results will be written back before calling gen_helper_check_ieee_exceptions, despite the placement of gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[]. We can simplify the entire implementation by having each FPOp helper call check_ieee_exceptions. For the moment this requires that all FPop helpers write to the TCG global cpu_fsr, so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-19-richard.henderson@linaro.org> --- target/sparc/helper.h | 119 +++++++++++---------- target/sparc/fop_helper.c | 215 ++++++++++++++++++++++++++++---------- target/sparc/translate.c | 14 --- 3 files changed, 219 insertions(+), 129 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index cc8db50d75..7c688edd62 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -35,81 +35,80 @@ DEF_HELPER_3(tsubcctv, tl, env, tl, tl) DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif -DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) -DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) -DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) -DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_RWG, i128, env, i128) -DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_2(fsqrts, 0, f32, env, f32) +DEF_HELPER_FLAGS_2(fsqrtd, 0, f64, env, f64) +DEF_HELPER_FLAGS_2(fsqrtq, 0, i128, env, i128) +DEF_HELPER_FLAGS_3(fcmps, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpes, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmped, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq, 0, tl, env, i128, i128) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmps_fcc1, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmps_fcc2, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmps_fcc3, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd_fcc1, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpd_fcc2, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpd_fcc3, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpes_fcc1, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes_fcc2, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes_fcc3, 0, tl, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmped_fcc1, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped_fcc2, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped_fcc3, 0, tl, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq_fcc1, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc2, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc3, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc1, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc2, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc3, 0, tl, env, i128, i128) #endif DEF_HELPER_2(raise_exception, noreturn, env, int) =20 -DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_RWG, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_RWG, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_RWG, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_RWG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(faddd, 0, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fsubd, 0, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fmuld, 0, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fdivd, 0, f64, env, f64, f64) =20 -DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_RWG, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_RWG, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fmulq, TCG_CALL_NO_RWG, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fdivq, TCG_CALL_NO_RWG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(faddq, 0, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fsubq, 0, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fmulq, 0, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fdivq, 0, i128, env, i128, i128) =20 -DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_RWG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_RWG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_RWG, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fadds, 0, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fsubs, 0, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fmuls, 0, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fdivs, 0, f32, env, f32, f32) =20 -DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32) -DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, i128, env, f64, f64) +DEF_HELPER_FLAGS_3(fsmuld, 0, f64, env, f32, f32) +DEF_HELPER_FLAGS_3(fdmulq, 0, i128, env, f64, f64) =20 -DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32) -DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, i128, env, s32) +DEF_HELPER_FLAGS_2(fitod, 0, f64, env, s32) +DEF_HELPER_FLAGS_2(fitoq, 0, i128, env, s32) =20 -DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32) +DEF_HELPER_FLAGS_2(fitos, 0, f32, env, s32) =20 #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64) -DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64) -DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, i128, env, s64) +DEF_HELPER_FLAGS_2(fxtos, 0, f32, env, s64) +DEF_HELPER_FLAGS_2(fxtod, 0, f64, env, s64) +DEF_HELPER_FLAGS_2(fxtoq, 0, i128, env, s64) #endif -DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) -DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) -DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) -DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, i128, env, f32) -DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_RWG, f64, env, i128) -DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, i128, env, f64) -DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) -DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) -DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i128) +DEF_HELPER_FLAGS_2(fdtos, 0, f32, env, f64) +DEF_HELPER_FLAGS_2(fstod, 0, f64, env, f32) +DEF_HELPER_FLAGS_2(fqtos, 0, f32, env, i128) +DEF_HELPER_FLAGS_2(fstoq, 0, i128, env, f32) +DEF_HELPER_FLAGS_2(fqtod, 0, f64, env, i128) +DEF_HELPER_FLAGS_2(fdtoq, 0, i128, env, f64) +DEF_HELPER_FLAGS_2(fstoi, 0, s32, env, f32) +DEF_HELPER_FLAGS_2(fdtoi, 0, s32, env, f64) +DEF_HELPER_FLAGS_2(fqtoi, 0, s32, env, i128) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32) -DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) -DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_RWG, s64, env, i128) +DEF_HELPER_FLAGS_2(fstox, 0, s64, env, f32) +DEF_HELPER_FLAGS_2(fdtox, 0, s64, env, f64) +DEF_HELPER_FLAGS_2(fqtox, 0, s64, env, i128) =20 DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 64f20e78f1..755117ea08 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -45,7 +45,7 @@ static inline Int128 f128_ret(float128 f) return u.i; } =20 -static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t= ra) +static void check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) { target_ulong status =3D get_float_exception_flags(&env->fp_status); target_ulong fsr =3D env->fsr; @@ -89,162 +89,265 @@ static target_ulong do_check_ieee_exceptions(CPUSPARC= State *env, uintptr_t ra) } } =20 - return fsr; + env->fsr =3D fsr; } =20 -target_ulong helper_check_ieee_exceptions(CPUSPARCState *env) +float32 helper_fadds(CPUSPARCState *env, float32 src1, float32 src2) { - return do_check_ieee_exceptions(env, GETPC()); + float32 ret =3D float32_add(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 -#define F_BINOP(name) \ - float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \ - float32 src2) \ - { \ - return float32_ ## name (src1, src2, &env->fp_status); \ - } \ - float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\ - float64 src2) \ - { \ - return float64_ ## name (src1, src2, &env->fp_status); \ - } \ - Int128 helper_f ## name ## q(CPUSPARCState * env, Int128 src1, \ - Int128 src2) \ - { \ - return f128_ret(float128_ ## name (f128_in(src1), f128_in(src2), \ - &env->fp_status)); \ - } +float32 helper_fsubs(CPUSPARCState *env, float32 src1, float32 src2) +{ + float32 ret =3D float32_sub(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} =20 -F_BINOP(add); -F_BINOP(sub); -F_BINOP(mul); -F_BINOP(div); -#undef F_BINOP +float32 helper_fmuls(CPUSPARCState *env, float32 src1, float32 src2) +{ + float32 ret =3D float32_mul(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float32 helper_fdivs(CPUSPARCState *env, float32 src1, float32 src2) +{ + float32 ret =3D float32_div(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_faddd(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_add(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fsubd(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_sub(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fmuld(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_mul(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fdivd(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_div(src1, src2, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +Int128 helper_faddq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + float128 ret =3D float128_add(f128_in(src1), f128_in(src2), &env->fp_s= tatus); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); +} + +Int128 helper_fsubq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + float128 ret =3D float128_sub(f128_in(src1), f128_in(src2), &env->fp_s= tatus); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); +} + +Int128 helper_fmulq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + float128 ret =3D float128_mul(f128_in(src1), f128_in(src2), &env->fp_s= tatus); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); +} + +Int128 helper_fdivq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + float128 ret =3D float128_div(f128_in(src1), f128_in(src2), &env->fp_s= tatus); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); +} =20 float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2) { - return float64_mul(float32_to_float64(src1, &env->fp_status), - float32_to_float64(src2, &env->fp_status), - &env->fp_status); + float64 ret =3D float64_mul(float32_to_float64(src1, &env->fp_status), + float32_to_float64(src2, &env->fp_status), + &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2) { - return f128_ret(float128_mul(float64_to_float128(src1, &env->fp_status= ), - float64_to_float128(src2, &env->fp_status= ), - &env->fp_status)); + float128 ret =3D float128_mul(float64_to_float128(src1, &env->fp_statu= s), + float64_to_float128(src2, &env->fp_status), + &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 /* Integer to float conversion. */ float32 helper_fitos(CPUSPARCState *env, int32_t src) { - return int32_to_float32(src, &env->fp_status); + float32 ret =3D int32_to_float32(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float64 helper_fitod(CPUSPARCState *env, int32_t src) { - return int32_to_float64(src, &env->fp_status); + float64 ret =3D int32_to_float64(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fitoq(CPUSPARCState *env, int32_t src) { - return f128_ret(int32_to_float128(src, &env->fp_status)); + float128 ret =3D int32_to_float128(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 #ifdef TARGET_SPARC64 float32 helper_fxtos(CPUSPARCState *env, int64_t src) { - return int64_to_float32(src, &env->fp_status); + float32 ret =3D int64_to_float32(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float64 helper_fxtod(CPUSPARCState *env, int64_t src) { - return int64_to_float64(src, &env->fp_status); + float64 ret =3D int64_to_float64(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fxtoq(CPUSPARCState *env, int64_t src) { - return f128_ret(int64_to_float128(src, &env->fp_status)); + float128 ret =3D int64_to_float128(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } #endif =20 /* floating point conversion */ float32 helper_fdtos(CPUSPARCState *env, float64 src) { - return float64_to_float32(src, &env->fp_status); + float32 ret =3D float64_to_float32(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float64 helper_fstod(CPUSPARCState *env, float32 src) { - return float32_to_float64(src, &env->fp_status); + float64 ret =3D float32_to_float64(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float32 helper_fqtos(CPUSPARCState *env, Int128 src) { - return float128_to_float32(f128_in(src), &env->fp_status); + float32 ret =3D float128_to_float32(f128_in(src), &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fstoq(CPUSPARCState *env, float32 src) { - return f128_ret(float32_to_float128(src, &env->fp_status)); + float128 ret =3D float32_to_float128(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 float64 helper_fqtod(CPUSPARCState *env, Int128 src) { - return float128_to_float64(f128_in(src), &env->fp_status); + float64 ret =3D float128_to_float64(f128_in(src), &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fdtoq(CPUSPARCState *env, float64 src) { - return f128_ret(float64_to_float128(src, &env->fp_status)); + float128 ret =3D float64_to_float128(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 /* Float to integer conversion. */ int32_t helper_fstoi(CPUSPARCState *env, float32 src) { - return float32_to_int32_round_to_zero(src, &env->fp_status); + int32_t ret =3D float32_to_int32_round_to_zero(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 int32_t helper_fdtoi(CPUSPARCState *env, float64 src) { - return float64_to_int32_round_to_zero(src, &env->fp_status); + int32_t ret =3D float64_to_int32_round_to_zero(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 int32_t helper_fqtoi(CPUSPARCState *env, Int128 src) { - return float128_to_int32_round_to_zero(f128_in(src), &env->fp_status); + int32_t ret =3D float128_to_int32_round_to_zero(f128_in(src), + &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 #ifdef TARGET_SPARC64 int64_t helper_fstox(CPUSPARCState *env, float32 src) { - return float32_to_int64_round_to_zero(src, &env->fp_status); + int64_t ret =3D float32_to_int64_round_to_zero(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 int64_t helper_fdtox(CPUSPARCState *env, float64 src) { - return float64_to_int64_round_to_zero(src, &env->fp_status); + int64_t ret =3D float64_to_int64_round_to_zero(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 int64_t helper_fqtox(CPUSPARCState *env, Int128 src) { - return float128_to_int64_round_to_zero(f128_in(src), &env->fp_status); + int64_t ret =3D float128_to_int64_round_to_zero(f128_in(src), + &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } #endif =20 float32 helper_fsqrts(CPUSPARCState *env, float32 src) { - return float32_sqrt(src, &env->fp_status); + float32 ret =3D float32_sqrt(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 float64 helper_fsqrtd(CPUSPARCState *env, float64 src) { - return float64_sqrt(src, &env->fp_status); + float64 ret =3D float64_sqrt(src, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; } =20 Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) { - return f128_ret(float128_sqrt(f128_in(src), &env->fp_status)); + float128 ret =3D float128_sqrt(f128_in(src), &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return f128_ret(ret); } =20 #define GEN_FCMP(name, size, FS, E) \ @@ -261,7 +364,8 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) ret =3D glue(size, _compare_quiet)(reg1, reg2, \ &env->fp_status); \ } \ - fsr =3D do_check_ieee_exceptions(env, GETPC()); \ + check_ieee_exceptions(env, GETPC()); \ + fsr =3D env->fsr; \ switch (ret) { \ case float_relation_unordered: \ fsr |=3D (FSR_FCC1 | FSR_FCC0) << FS; \ @@ -292,7 +396,8 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) ret =3D glue(size, _compare_quiet)(src1, src2, \ &env->fp_status); \ } \ - fsr =3D do_check_ieee_exceptions(env, GETPC()); \ + check_ieee_exceptions(env, GETPC()); \ + fsr =3D env->fsr; \ switch (ret) { \ case float_relation_unordered: \ fsr |=3D (FSR_FCC1 | FSR_FCC0) << FS; \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 67bac6f65f..25f93ec44a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4526,7 +4526,6 @@ static bool do_env_ff(DisasContext *dc, arg_r_r *a, =20 tmp =3D gen_load_fpr_F(dc, a->rs); func(tmp, tcg_env, tmp); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, tmp); return advance_pc(dc); } @@ -4548,7 +4547,6 @@ static bool do_env_fd(DisasContext *dc, arg_r_r *a, dst =3D tcg_temp_new_i32(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); return advance_pc(dc); } @@ -4591,7 +4589,6 @@ static bool do_env_dd(DisasContext *dc, arg_r_r *a, dst =3D gen_dest_fpr_D(dc, a->rd); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4613,7 +4610,6 @@ static bool do_env_df(DisasContext *dc, arg_r_r *a, dst =3D gen_dest_fpr_D(dc, a->rd); src =3D gen_load_fpr_F(dc, a->rs); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4659,7 +4655,6 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, =20 t =3D gen_load_fpr_Q(dc, a->rs); func(t, tcg_env, t); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_Q(dc, a->rd, t); return advance_pc(dc); } @@ -4682,7 +4677,6 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, src =3D gen_load_fpr_Q(dc, a->rs); dst =3D tcg_temp_new_i32(); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); return advance_pc(dc); } @@ -4706,7 +4700,6 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, src =3D gen_load_fpr_Q(dc, a->rs); dst =3D gen_dest_fpr_D(dc, a->rd); func(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4727,7 +4720,6 @@ static bool do_env_qf(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_F(dc, a->rs); dst =3D tcg_temp_new_i128(); func(dst, tcg_env, src); @@ -4751,7 +4743,6 @@ static bool do_env_qd(DisasContext *dc, arg_r_r *a, return true; } =20 - gen_op_clear_ieee_excp_and_FTT(); src =3D gen_load_fpr_D(dc, a->rs); dst =3D tcg_temp_new_i128(); func(dst, tcg_env, src); @@ -4803,7 +4794,6 @@ static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); func(src1, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, src1); return advance_pc(dc); } @@ -4898,7 +4888,6 @@ static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); func(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4924,7 +4913,6 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r = *a) src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); gen_helper_fsmuld(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } @@ -4964,7 +4952,6 @@ static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, src1 =3D gen_load_fpr_Q(dc, a->rs1); src2 =3D gen_load_fpr_Q(dc, a->rs2); func(src1, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_Q(dc, a->rd, src1); return advance_pc(dc); } @@ -4990,7 +4977,6 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r = *a) src2 =3D gen_load_fpr_D(dc, a->rs2); dst =3D tcg_temp_new_i128(); gen_helper_fdmulq(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_Q(dc, a->rd, dst); return advance_pc(dc); } --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id je5-20020a170903264500b001d8a80cbb15sm752059plb.238.2024.02.01.21.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:55:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853342; x=1707458142; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ULiNZjMoC+ixiCPJhcdGEZXbCkj2T5rK3rV/1qTi1po=; b=u79Jo7YIqDuLXv+XVa4GCyQV+PT+kXd1jBRA/Yf6xvEtcTVq5ZgM0myPzwxndIkJf6 WPcshgVn5xN90YwlPUkcg/mLEkJcZdzsVnYPe8fVufUqpXiMWSNUBL/LPyn/YDgHoJx1 EjTql9ZsQxuFlWuYP/yqBH6Ru3KLa9nMB8qMbfXJnfPMVB4raGhkc3HmDSFilgtldMNa Gqe0fAlJbFs5xdxjCWZ9eaYdCkVVDPT4KqTabRMSEEm57pDRBXkIm2DG+zYuvsksFjOk Vp0JQ691qciy+HbTD5TmV974Ouru1eeonVhTVfOiMGQ0XCDGkDWthjZHNNRlYpuky/FU cpgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853342; x=1707458142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ULiNZjMoC+ixiCPJhcdGEZXbCkj2T5rK3rV/1qTi1po=; b=ovCYxH2S2hepYJYEE7yfw3J8E3tkoaUsD/Bt32O8y2gqBSyaYIJSBBDXETg8OYmk53 f93zsABbGJ2OnFDtPNKqN/iRG8/USH0C7D+cZ6tStY+L7OleBwNLm4yyi9YbLTdwd+xY buAQNhfGWI8CQ7ikV9OFFB7Q/C8xYBKmvoy+H6R9evS31hMLqLxsm3mzEqoRMrNWy9ge DojofZ7lUPZCmQlvcjrgVia1yiFxFX5obaqj6rmU+tNRleTcmuevYLK+B8/0CY4R+jfK du+dsbMXkTRoS7OXTJ3IV30R2sISDm8aNBYO1DKQLBVWLDSOxpgt4qJFrQXRgOEVVP20 C74A== X-Gm-Message-State: AOJu0YwkWNibOlJQDGTzD6vQT/xBvr68IBGPYCQ3kE1BT4lIOWKkklRl 7AkxHgw8QZwGHs7MGjzK+S2apKfIBNT9ki5Fg7/KCAP6j8V6DztvSBZebmv3RVDXgmNiyxSpv38 NZFc= X-Google-Smtp-Source: AGHT+IEeVfdJzDAMouV3533MpWnvoDaurVMMDayuDEpske9cP5pKJCxOeXcmlC+Z5II5Cv+lSlhY+A== X-Received: by 2002:a17:902:bf4c:b0:1d7:3067:aab5 with SMTP id u12-20020a170902bf4c00b001d73067aab5mr6327651pls.57.1706853341769; Thu, 01 Feb 2024 21:55:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 54/57] target/sparc: Split cexc and ftt from env->fsr Date: Fri, 2 Feb 2024 15:50:33 +1000 Message-Id: <20240202055036.684176-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853539851100001 Content-Type: text/plain; charset="utf-8" These two fields are adjusted by all FPop insns. Having them separate makes it easier to set without masking. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org> --- target/sparc/cpu.h | 7 +++++- target/sparc/helper.h | 2 +- target/sparc/fop_helper.c | 46 ++++++++++++++++++--------------------- target/sparc/translate.c | 31 ++++++++++++++++---------- 4 files changed, 48 insertions(+), 38 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 216155d231..c5be9e37de 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -176,6 +176,7 @@ enum { #define FSR_DZM (1ULL << 24) #define FSR_NXM (1ULL << 23) #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) +#define FSR_TEM_SHIFT 23 =20 #define FSR_NVA (1ULL << 9) #define FSR_OFA (1ULL << 8) @@ -183,6 +184,7 @@ enum { #define FSR_DZA (1ULL << 6) #define FSR_NXA (1ULL << 5) #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) +#define FSR_AEXC_SHIFT 5 =20 #define FSR_NVC (1ULL << 4) #define FSR_OFC (1ULL << 3) @@ -464,7 +466,10 @@ struct CPUArchState { target_ulong cond; /* conditional branch result (XXX: save it in a temporary register when possible) */ =20 - target_ulong fsr; /* FPU state register */ + /* FPU State Register, in parts */ + target_ulong fsr; /* rm, tem, aexc, fcc* */ + uint32_t fsr_cexc_ftt; /* cexc, ftt */ + CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted from PSR) */ diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 7c688edd62..7466164468 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,7 +36,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, = int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) -DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(set_fsr_noftt, 0, void, env, tl) DEF_HELPER_FLAGS_2(fsqrts, 0, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, 0, f64, env, f64) DEF_HELPER_FLAGS_2(fsqrtq, 0, i128, env, i128) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 755117ea08..ac30f88810 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -48,9 +48,7 @@ static inline Int128 f128_ret(float128 f) static void check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) { target_ulong status =3D get_float_exception_flags(&env->fp_status); - target_ulong fsr =3D env->fsr; - - fsr &=3D FSR_FTT_CEXC_NMASK; + uint32_t cexc =3D 0; =20 if (unlikely(status)) { /* Keep exception flags clear for next time. */ @@ -58,38 +56,33 @@ static void check_ieee_exceptions(CPUSPARCState *env, u= intptr_t ra) =20 /* Copy IEEE 754 flags into FSR */ if (status & float_flag_invalid) { - fsr |=3D FSR_NVC; + cexc |=3D FSR_NVC; } if (status & float_flag_overflow) { - fsr |=3D FSR_OFC; + cexc |=3D FSR_OFC; } if (status & float_flag_underflow) { - fsr |=3D FSR_UFC; + cexc |=3D FSR_UFC; } if (status & float_flag_divbyzero) { - fsr |=3D FSR_DZC; + cexc |=3D FSR_DZC; } if (status & float_flag_inexact) { - fsr |=3D FSR_NXC; + cexc |=3D FSR_NXC; } =20 - if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) { - CPUState *cs =3D env_cpu(env); - - /* Unmasked exception, generate a trap. Note that while - the helper is marked as NO_WG, we can get away with - writing to cpu state along the exception path, since - TCG generated code will never see the write. */ - env->fsr =3D fsr | FSR_FTT_IEEE_EXCP; - cs->exception_index =3D TT_FP_EXCP; - cpu_loop_exit_restore(cs, ra); - } else { - /* Accumulate exceptions */ - fsr |=3D (fsr & FSR_CEXC_MASK) << 5; + if (cexc & (env->fsr >> FSR_TEM_SHIFT)) { + /* Unmasked exception, generate an IEEE trap. */ + env->fsr_cexc_ftt =3D cexc | FSR_FTT_IEEE_EXCP; + cpu_raise_exception_ra(env, TT_FP_EXCP, ra); } + + /* Accumulate exceptions */ + env->fsr |=3D cexc << FSR_AEXC_SHIFT; } =20 - env->fsr =3D fsr; + /* No trap, so FTT is cleared. */ + env->fsr_cexc_ftt =3D cexc; } =20 float32 helper_fadds(CPUSPARCState *env, float32 src1, float32 src2) @@ -456,7 +449,7 @@ GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); =20 target_ulong cpu_get_fsr(CPUSPARCState *env) { - target_ulong fsr =3D env->fsr; + target_ulong fsr =3D env->fsr | env->fsr_cexc_ftt; =20 /* VER is kept completely separate until re-assembly. */ fsr |=3D env->def.fpu_version; @@ -473,7 +466,7 @@ static void set_fsr_nonsplit(CPUSPARCState *env, target= _ulong fsr) { int rnd_mode; =20 - env->fsr =3D fsr & ~FSR_VER_MASK; + env->fsr =3D fsr & ~(FSR_VER_MASK | FSR_CEXC_MASK | FSR_FTT_MASK); =20 switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: @@ -495,10 +488,13 @@ static void set_fsr_nonsplit(CPUSPARCState *env, targ= et_ulong fsr) =20 void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) { + env->fsr_cexc_ftt =3D fsr & (FSR_CEXC_MASK | FSR_FTT_MASK); set_fsr_nonsplit(env, fsr); } =20 -void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) +void helper_set_fsr_noftt(CPUSPARCState *env, target_ulong fsr) { + env->fsr_cexc_ftt &=3D FSR_FTT_MASK; + env->fsr_cexc_ftt |=3D fsr & FSR_CEXC_MASK; set_fsr_nonsplit(env, fsr); } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 25f93ec44a..5b9bbeb8ff 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1199,7 +1199,8 @@ static bool gen_compare_reg(DisasCompare *cmp, int co= nd, TCGv r_src) =20 static void gen_op_clear_ieee_excp_and_FTT(void) { - tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); + tcg_gen_st_i32(tcg_constant_i32(0), tcg_env, + offsetof(CPUSPARCState, fsr_cexc_ftt)); } =20 static void gen_op_fmovs(TCGv_i32 dst, TCGv_i32 src) @@ -1400,10 +1401,15 @@ static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs= 1, TCGv_i128 r_rs2) } #endif =20 -static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags) +static void gen_op_fpexception_im(DisasContext *dc, int ftt) { - tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); - tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); + /* + * CEXC is only set when succesfully completing an FPop, + * or when raising FSR_FTT_IEEE_EXCP, i.e. check_ieee_exception. + * Thus we can simply store FTT into this field. + */ + tcg_gen_st_i32(tcg_constant_i32(ftt), tcg_env, + offsetof(CPUSPARCState, fsr_cexc_ftt)); gen_exception(dc, TT_FP_EXCP); } =20 @@ -4395,19 +4401,22 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ= *a) static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop, target_ulong new_mask, target_ulong old_mask) { - TCGv tmp, addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv tnew, told; + if (addr =3D=3D NULL) { return false; } if (gen_trap_ifnofpu(dc)) { return true; } - tmp =3D tcg_temp_new(); - tcg_gen_qemu_ld_tl(tmp, addr, dc->mem_idx, mop | MO_ALIGN); - tcg_gen_andi_tl(tmp, tmp, new_mask); - tcg_gen_andi_tl(cpu_fsr, cpu_fsr, old_mask); - tcg_gen_or_tl(cpu_fsr, cpu_fsr, tmp); - gen_helper_set_fsr(tcg_env, cpu_fsr); + tnew =3D tcg_temp_new(); + told =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(tnew, addr, dc->mem_idx, mop | MO_ALIGN); + tcg_gen_andi_tl(tnew, tnew, new_mask); + tcg_gen_andi_tl(told, cpu_fsr, old_mask); + tcg_gen_or_tl(tnew, tnew, told); + gen_helper_set_fsr_noftt(tcg_env, tnew); return advance_pc(dc); } =20 --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id je5-20020a170903264500b001d8a80cbb15sm752059plb.238.2024.02.01.21.55.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:55:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853344; x=1707458144; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xbdAL5DvJKQPWcY3wsaw848CgsUHDg3QTYtvSkzuHmY=; b=u+zx+IQXgSO1Wu0qMfytQRcrax1KJL98VJ/QE74AbX1QQbyG8dwkYB/J0YA7NxdQr4 x+391POU4O5AHy/GKTwUpruOpEVE15/UaHLioriqZ1VvD8SgdwUyOaDpA3xgIzZn4fgR oBCZeaXSU33yCmgrz0sx0fgMnW9WdGacGRksFgBlJX/gpwAN5i3ZX96RiRh4IJClfi2t ms5zF3qPudqb2rKi1Zp3fYzNPMAubPQyoPgxbrhQS1iLOFCekyRYKfGsGAGnk9M2fjhw 5mZu+F/lISwTSZnEkoVZCliieqDGPKg7usm8vkDw7PGgcRcsapKLlpaYAEswXOCHkUMP VmzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853344; x=1707458144; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xbdAL5DvJKQPWcY3wsaw848CgsUHDg3QTYtvSkzuHmY=; b=fmSMnTQ6XFjwcEDWGa7QTB2t+Q0hOb6+hGVLtRMxVeRJ/E0VMjiszpFBtjTTpdUbg9 5VisY+kORdv8TbTDRprYDcXSL95u0SedwcwQZ9iVCR9LjgOJCWOZE4/J00Tq8QfQIwa/ F5el3ss7G8rdlKV+J0ecrElVB9wcialcO8JAsNbJnGWvUih3ZpuM3eXkO+1kTr67+8z0 jzjpSGh/u9u2mN8pYo1haUh9fBubQ0TZRxf0NONI29YlA7QXPGefp4wrOxMsLpOtUwDZ zCHlFz10IyFsRN+2KVzD1CJiFSj6QkmtJYRYvf2enqLJMq0GrK0HEYvufsYUDfA1+7fg /zJQ== X-Gm-Message-State: AOJu0YxYjEFwbYnX6s8Nex95ntXzwYTitQfDzQhiyJhW5mE13YYXnsW8 vyM3kUVecwcFY4Me9mIOiEyjkNwr1OwxE61yGzSO8yf+om78xhG4EqyE4U1wuOtBZ/IRGVn0Tzk ZZ+g= X-Google-Smtp-Source: AGHT+IF1wcFumyJ9BNypAtuMrDf1sCL28TCMSeFpDp76X1tFvneKBdzpT02SXs65B6T9J1zyP44AhA== X-Received: by 2002:a17:902:d509:b0:1d8:ef9e:b436 with SMTP id b9-20020a170902d50900b001d8ef9eb436mr1633932plg.22.1706853343889; Thu, 01 Feb 2024 21:55:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 55/57] target/sparc: Remove cpu_fsr Date: Fri, 2 Feb 2024 15:50:34 +1000 Message-Id: <20240202055036.684176-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853383342100008 Content-Type: text/plain; charset="utf-8" Drop this field as a tcg global, loading it explicitly in the few places required. This means that all FPop helpers may once again be TCG_CALL_NO_WG. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org> --- target/sparc/helper.h | 120 +++++++++++++++++++------------------- target/sparc/fop_helper.c | 9 ++- target/sparc/translate.c | 98 ++++++++++++++++--------------- 3 files changed, 114 insertions(+), 113 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 7466164468..c8e14fe371 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,79 +36,79 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl= , int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) -DEF_HELPER_FLAGS_2(set_fsr_noftt, 0, void, env, tl) -DEF_HELPER_FLAGS_2(fsqrts, 0, f32, env, f32) -DEF_HELPER_FLAGS_2(fsqrtd, 0, f64, env, f64) -DEF_HELPER_FLAGS_2(fsqrtq, 0, i128, env, i128) -DEF_HELPER_FLAGS_3(fcmps, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_2(set_fsr_noftt, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_WG, f32, env, f32) +DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_WG, f64, env, f64) +DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_WG, i128, env, i128) +DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, void, env, i128, i128) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(fcmps_fcc1, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc2, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc3, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd_fcc1, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc2, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc3, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes_fcc1, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc2, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc3, 0, tl, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped_fcc1, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc2, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc3, 0, tl, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq_fcc1, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc2, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc3, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc1, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc2, 0, tl, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc3, 0, tl, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128) #endif DEF_HELPER_2(raise_exception, noreturn, env, int) =20 -DEF_HELPER_FLAGS_3(faddd, 0, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fsubd, 0, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fmuld, 0, f64, env, f64, f64) -DEF_HELPER_FLAGS_3(fdivd, 0, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64) =20 -DEF_HELPER_FLAGS_3(faddq, 0, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fsubq, 0, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fmulq, 0, i128, env, i128, i128) -DEF_HELPER_FLAGS_3(fdivq, 0, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fmulq, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(fdivq, TCG_CALL_NO_WG, i128, env, i128, i128) =20 -DEF_HELPER_FLAGS_3(fadds, 0, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fsubs, 0, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fmuls, 0, f32, env, f32, f32) -DEF_HELPER_FLAGS_3(fdivs, 0, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32) =20 -DEF_HELPER_FLAGS_3(fsmuld, 0, f64, env, f32, f32) -DEF_HELPER_FLAGS_3(fdmulq, 0, i128, env, f64, f64) +DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_WG, f64, env, f32, f32) +DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_WG, i128, env, f64, f64) =20 -DEF_HELPER_FLAGS_2(fitod, 0, f64, env, s32) -DEF_HELPER_FLAGS_2(fitoq, 0, i128, env, s32) +DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_WG, f64, env, s32) +DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_WG, i128, env, s32) =20 -DEF_HELPER_FLAGS_2(fitos, 0, f32, env, s32) +DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_WG, f32, env, s32) =20 #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_2(fxtos, 0, f32, env, s64) -DEF_HELPER_FLAGS_2(fxtod, 0, f64, env, s64) -DEF_HELPER_FLAGS_2(fxtoq, 0, i128, env, s64) +DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_WG, f32, env, s64) +DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_WG, f64, env, s64) +DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_WG, i128, env, s64) #endif -DEF_HELPER_FLAGS_2(fdtos, 0, f32, env, f64) -DEF_HELPER_FLAGS_2(fstod, 0, f64, env, f32) -DEF_HELPER_FLAGS_2(fqtos, 0, f32, env, i128) -DEF_HELPER_FLAGS_2(fstoq, 0, i128, env, f32) -DEF_HELPER_FLAGS_2(fqtod, 0, f64, env, i128) -DEF_HELPER_FLAGS_2(fdtoq, 0, i128, env, f64) -DEF_HELPER_FLAGS_2(fstoi, 0, s32, env, f32) -DEF_HELPER_FLAGS_2(fdtoi, 0, s32, env, f64) -DEF_HELPER_FLAGS_2(fqtoi, 0, s32, env, i128) +DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_WG, f32, env, f64) +DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_WG, f64, env, f32) +DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_WG, f32, env, i128) +DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_WG, i128, env, f32) +DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_WG, f64, env, i128) +DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_WG, i128, env, f64) +DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_WG, s32, env, f32) +DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_WG, s32, env, f64) +DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_WG, s32, env, i128) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_2(fstox, 0, s64, env, f32) -DEF_HELPER_FLAGS_2(fdtox, 0, s64, env, f64) -DEF_HELPER_FLAGS_2(fqtox, 0, s64, env, i128) +DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_WG, s64, env, f32) +DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_WG, s64, env, f64) +DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128) =20 DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index ac30f88810..796f448bfd 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -344,8 +344,7 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) } =20 #define GEN_FCMP(name, size, FS, E) \ - target_ulong glue(helper_, name) (CPUSPARCState *env, \ - Int128 src1, Int128 src2) \ + void glue(helper_, name)(CPUSPARCState *env, Int128 src1, Int128 src2)= \ { \ float128 reg1 =3D f128_in(src1); \ float128 reg2 =3D f128_in(src2); \ @@ -376,10 +375,10 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) fsr &=3D ~((FSR_FCC1 | FSR_FCC0) << FS); \ break; \ } \ - return fsr; \ + env->fsr =3D fsr; \ } #define GEN_FCMP_T(name, size, FS, E) \ - target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size s= rc2)\ + void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \ { \ FloatRelation ret; \ target_ulong fsr; \ @@ -407,7 +406,7 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) fsr &=3D ~((FSR_FCC1 | FSR_FCC0) << FS); \ break; \ } \ - return fsr; \ + env->fsr =3D fsr; \ } =20 GEN_FCMP_T(fcmps, float32, 0, 0); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5b9bbeb8ff..cf8cfe5cc4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -99,7 +99,7 @@ =20 /* global register indexes */ static TCGv_ptr cpu_regwptr; -static TCGv cpu_fsr, cpu_pc, cpu_npc; +static TCGv cpu_pc, cpu_npc; static TCGv cpu_regs[32]; static TCGv cpu_y; static TCGv cpu_tbr; @@ -1097,7 +1097,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int = cond) { unsigned int offset; - TCGv r_dst; + TCGv r_dst, fsr; =20 /* For now we still generate a straight boolean result. */ cmp->cond =3D TCG_COND_NE; @@ -1120,54 +1120,56 @@ static void gen_fcompare(DisasCompare *cmp, unsigne= d int cc, unsigned int cond) break; } =20 + fsr =3D tcg_temp_new(); + tcg_gen_ld_tl(fsr, tcg_env, offsetof(CPUSPARCState, fsr)); switch (cond) { case 0x0: gen_op_eval_bn(r_dst); break; case 0x1: - gen_op_eval_fbne(r_dst, cpu_fsr, offset); + gen_op_eval_fbne(r_dst, fsr, offset); break; case 0x2: - gen_op_eval_fblg(r_dst, cpu_fsr, offset); + gen_op_eval_fblg(r_dst, fsr, offset); break; case 0x3: - gen_op_eval_fbul(r_dst, cpu_fsr, offset); + gen_op_eval_fbul(r_dst, fsr, offset); break; case 0x4: - gen_op_eval_fbl(r_dst, cpu_fsr, offset); + gen_op_eval_fbl(r_dst, fsr, offset); break; case 0x5: - gen_op_eval_fbug(r_dst, cpu_fsr, offset); + gen_op_eval_fbug(r_dst, fsr, offset); break; case 0x6: - gen_op_eval_fbg(r_dst, cpu_fsr, offset); + gen_op_eval_fbg(r_dst, fsr, offset); break; case 0x7: - gen_op_eval_fbu(r_dst, cpu_fsr, offset); + gen_op_eval_fbu(r_dst, fsr, offset); break; case 0x8: gen_op_eval_ba(r_dst); break; case 0x9: - gen_op_eval_fbe(r_dst, cpu_fsr, offset); + gen_op_eval_fbe(r_dst, fsr, offset); break; case 0xa: - gen_op_eval_fbue(r_dst, cpu_fsr, offset); + gen_op_eval_fbue(r_dst, fsr, offset); break; case 0xb: - gen_op_eval_fbge(r_dst, cpu_fsr, offset); + gen_op_eval_fbge(r_dst, fsr, offset); break; case 0xc: - gen_op_eval_fbuge(r_dst, cpu_fsr, offset); + gen_op_eval_fbuge(r_dst, fsr, offset); break; case 0xd: - gen_op_eval_fble(r_dst, cpu_fsr, offset); + gen_op_eval_fble(r_dst, fsr, offset); break; case 0xe: - gen_op_eval_fbule(r_dst, cpu_fsr, offset); + gen_op_eval_fbule(r_dst, fsr, offset); break; case 0xf: - gen_op_eval_fbo(r_dst, cpu_fsr, offset); + gen_op_eval_fbo(r_dst, fsr, offset); break; } } @@ -1264,16 +1266,16 @@ static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1,= TCGv_i32 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1282,16 +1284,16 @@ static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1,= TCGv_i64 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1300,16 +1302,16 @@ static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1= , TCGv_i128 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1318,16 +1320,16 @@ static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1= , TCGv_i32 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1336,16 +1338,16 @@ static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1= , TCGv_i64 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1354,16 +1356,16 @@ static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs= 1, TCGv_i128 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq_fcc1(tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq_fcc2(tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq_fcc3(tcg_env, r_rs1, r_rs2); break; } } @@ -1372,32 +1374,32 @@ static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs= 1, TCGv_i128 r_rs2) =20 static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) { - gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmps(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { - gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpd(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { - gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpq(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) { - gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpes(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { - gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmped(tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) { - gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); + gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2); } #endif =20 @@ -4413,8 +4415,9 @@ static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a,= MemOp mop, tnew =3D tcg_temp_new(); told =3D tcg_temp_new(); tcg_gen_qemu_ld_tl(tnew, addr, dc->mem_idx, mop | MO_ALIGN); + tcg_gen_ld_tl(told, tcg_env, offsetof(CPUSPARCState, fsr)); tcg_gen_andi_tl(tnew, tnew, new_mask); - tcg_gen_andi_tl(told, cpu_fsr, old_mask); + tcg_gen_andi_tl(told, told, old_mask); tcg_gen_or_tl(tnew, tnew, told); gen_helper_set_fsr_noftt(tcg_env, tnew); return advance_pc(dc); @@ -5342,7 +5345,6 @@ void sparc_tcg_init(void) { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" }, { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" }, { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, - { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" }, { 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id je5-20020a170903264500b001d8a80cbb15sm752059plb.238.2024.02.01.21.55.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:55:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853346; x=1707458146; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KteVrj8gst013uyEXcP3e0N3hZHJ2ci9f+j/2/rpEZc=; b=hhFcpSBpUS7cZfLiMhSZXQJkotr+tSJmE+HIBBb64TsVm7FbwKUwIsQqWuAWPO9iLQ Q/UyOFRHzprRbpZ2fW95xt94XDnB+w3dDKteluOo6NUp0do6DEzTPXKD6rJhRzKI8E3c +ouryT3V3NGzdF+iZClOJaSnFhO0GPHDxbTwffa3HttY09Z6I0oCas5OcREo/1NHIoLJ fUvcG4fDtYyTbl/7v9qW1MiuFlsiWiEv+wp7embQusllBB0+hwHLGWNEpwqHSUXbJ/wG bB0UWGvGPmpTdxv1648SM8jry/ymUZjW1CFXm3rxBftON7wvkNj8Ru4o36U2s1f06MtF WonA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853346; x=1707458146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KteVrj8gst013uyEXcP3e0N3hZHJ2ci9f+j/2/rpEZc=; b=lJjBwTqD/iUu3Zw+nV88uBEKQAdUCPZGSbQO5/uF4sNJx6q5cnm0KcMjyKxa1aXSDp beW847o1Y4w5F+DDRlm1VTCqICRerV1/G/YwIm/WyMPchh8LxFrH22JxniOwv5m1Lofn yr/t7TbKwGJB4c1eDEKRIvMag5OwjEJCks2BiAej017Nm8irn1omuxqs4mGOJpzA7y4O mP16fSA1TOp4drjwlWi1lIR/nphkp5e0RlFC8nomU8Pl0PjyCYABMAkivJL1/CN/ccrR 4NmiYV+z62LHMUif647to/k3NSTfcmSjnM/Q5Crt/S6X4+IQVlzhzQrOQIbeLFZHkFBp Sw6g== X-Gm-Message-State: AOJu0YxIHraCs1GU+pXsxbN3+lYs5yIrEdP9ilA1eTrAlwu4M9w60ZwU FjA7tTAxAMA8yyRBsrRHrFLyD/EYMki213DeJsZoQQg/B8oDk7/dM8M74YOv6Zckw9eisvWpfFx /FoY= X-Google-Smtp-Source: AGHT+IEJ30lbbjkVxbXFXxg2WtpfZLKdlkpadrQA67dc90cJMaa8WDslvzfl+FbqTYND4gi1N5xYJg== X-Received: by 2002:a17:902:fc85:b0:1d9:6e29:ea86 with SMTP id mf5-20020a170902fc8500b001d96e29ea86mr1538662plb.64.1706853346029; Thu, 01 Feb 2024 21:55:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 56/57] target/sparc: Split fcc out of env->fsr Date: Fri, 2 Feb 2024 15:50:35 +1000 Message-Id: <20240202055036.684176-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853537777100003 Content-Type: text/plain; charset="utf-8" Represent each fcc field separately from the rest of fsr. This vastly simplifies floating-point comparisons. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org> --- target/sparc/cpu.h | 20 +- target/sparc/helper.h | 34 +-- target/sparc/fop_helper.c | 169 ++++++------- target/sparc/translate.c | 503 +++++++++----------------------------- 4 files changed, 201 insertions(+), 525 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index c5be9e37de..986c7217ed 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -31,8 +31,10 @@ =20 #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 +#define TARGET_FCCREGS 1 #else #define TARGET_DPREGS 32 +#define TARGET_FCCREGS 4 #endif =20 /*#define EXCP_INTERRUPT 0x100*/ @@ -203,24 +205,19 @@ enum { #ifdef TARGET_SPARC64 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL -#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL -#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL -#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL #else #define FSR_FTT_NMASK 0xfffe3fffULL #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL -#define FSR_LDFSR_OLDMASK 0x000fc000ULL #endif -#define FSR_LDFSR_MASK 0xcfc00fffULL #define FSR_FTT_IEEE_EXCP (1ULL << 14) #define FSR_FTT_UNIMPFPOP (3ULL << 14) #define FSR_FTT_SEQ_ERROR (4ULL << 14) #define FSR_FTT_INVAL_FPR (6ULL << 14) =20 -#define FSR_FCC1_SHIFT 11 -#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) -#define FSR_FCC0_SHIFT 10 -#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) +#define FSR_FCC0_SHIFT 10 +#define FSR_FCC1_SHIFT 32 +#define FSR_FCC2_SHIFT 34 +#define FSR_FCC3_SHIFT 36 =20 /* MMU */ #define MMU_E (1<<0) @@ -467,8 +464,9 @@ struct CPUArchState { temporary register when possible) */ =20 /* FPU State Register, in parts */ - target_ulong fsr; /* rm, tem, aexc, fcc* */ - uint32_t fsr_cexc_ftt; /* cexc, ftt */ + uint32_t fsr; /* rm, tem, aexc */ + uint32_t fsr_cexc_ftt; /* cexc, ftt */ + uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ =20 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted diff --git a/target/sparc/helper.h b/target/sparc/helper.h index c8e14fe371..6a42ba4e9e 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -36,36 +36,16 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl= , int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) -DEF_HELPER_FLAGS_2(set_fsr_noftt, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(set_fsr_nofcc_noftt, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_WG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_WG, f64, env, f64) DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_WG, i128, env, i128) -DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, void, env, i128, i128) -#ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, void, env, f32, f32) -DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, void, env, f64, f64) -DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128) -DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128) -#endif +DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) +DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_2(raise_exception, noreturn, env, int) =20 DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 796f448bfd..1205a599ef 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -343,113 +343,80 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) return f128_ret(ret); } =20 -#define GEN_FCMP(name, size, FS, E) \ - void glue(helper_, name)(CPUSPARCState *env, Int128 src1, Int128 src2)= \ - { \ - float128 reg1 =3D f128_in(src1); \ - float128 reg2 =3D f128_in(src2); \ - FloatRelation ret; \ - target_ulong fsr; \ - if (E) { \ - ret =3D glue(size, _compare)(reg1, reg2, &env->fp_status); \ - } else { \ - ret =3D glue(size, _compare_quiet)(reg1, reg2, \ - &env->fp_status); \ - } \ - check_ieee_exceptions(env, GETPC()); \ - fsr =3D env->fsr; \ - switch (ret) { \ - case float_relation_unordered: \ - fsr |=3D (FSR_FCC1 | FSR_FCC0) << FS; \ - fsr |=3D FSR_NVA; \ - break; \ - case float_relation_less: \ - fsr &=3D ~(FSR_FCC1) << FS; \ - fsr |=3D FSR_FCC0 << FS; \ - break; \ - case float_relation_greater: \ - fsr &=3D ~(FSR_FCC0) << FS; \ - fsr |=3D FSR_FCC1 << FS; \ - break; \ - default: \ - fsr &=3D ~((FSR_FCC1 | FSR_FCC0) << FS); \ - break; \ - } \ - env->fsr =3D fsr; \ - } -#define GEN_FCMP_T(name, size, FS, E) \ - void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \ - { \ - FloatRelation ret; \ - target_ulong fsr; \ - if (E) { \ - ret =3D glue(size, _compare)(src1, src2, &env->fp_status); \ - } else { \ - ret =3D glue(size, _compare_quiet)(src1, src2, \ - &env->fp_status); \ - } \ - check_ieee_exceptions(env, GETPC()); \ - fsr =3D env->fsr; \ - switch (ret) { \ - case float_relation_unordered: \ - fsr |=3D (FSR_FCC1 | FSR_FCC0) << FS; \ - break; \ - case float_relation_less: \ - fsr &=3D ~(FSR_FCC1 << FS); \ - fsr |=3D FSR_FCC0 << FS; \ - break; \ - case float_relation_greater: \ - fsr &=3D ~(FSR_FCC0 << FS); \ - fsr |=3D FSR_FCC1 << FS; \ - break; \ - default: \ - fsr &=3D ~((FSR_FCC1 | FSR_FCC0) << FS); \ - break; \ - } \ - env->fsr =3D fsr; \ +static uint32_t finish_fcmp(CPUSPARCState *env, FloatRelation r, uintptr_t= ra) +{ + check_ieee_exceptions(env, ra); + + /* + * FCC values: + * 0 =3D + * 1 < + * 2 > + * 3 unordered + */ + switch (r) { + case float_relation_equal: + return 0; + case float_relation_less: + return 1; + case float_relation_greater: + return 2; + case float_relation_unordered: + env->fsr |=3D FSR_NVA; + return 3; } + g_assert_not_reached(); +} =20 -GEN_FCMP_T(fcmps, float32, 0, 0); -GEN_FCMP_T(fcmpd, float64, 0, 0); +uint32_t helper_fcmps(CPUSPARCState *env, float32 src1, float32 src2) +{ + FloatRelation r =3D float32_compare_quiet(src1, src2, &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -GEN_FCMP_T(fcmpes, float32, 0, 1); -GEN_FCMP_T(fcmped, float64, 0, 1); +uint32_t helper_fcmpes(CPUSPARCState *env, float32 src1, float32 src2) +{ + FloatRelation r =3D float32_compare(src1, src2, &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -GEN_FCMP(fcmpq, float128, 0, 0); -GEN_FCMP(fcmpeq, float128, 0, 1); +uint32_t helper_fcmpd(CPUSPARCState *env, float64 src1, float64 src2) +{ + FloatRelation r =3D float64_compare_quiet(src1, src2, &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -#ifdef TARGET_SPARC64 -GEN_FCMP_T(fcmps_fcc1, float32, 22, 0); -GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0); -GEN_FCMP(fcmpq_fcc1, float128, 22, 0); +uint32_t helper_fcmped(CPUSPARCState *env, float64 src1, float64 src2) +{ + FloatRelation r =3D float64_compare(src1, src2, &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -GEN_FCMP_T(fcmps_fcc2, float32, 24, 0); -GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0); -GEN_FCMP(fcmpq_fcc2, float128, 24, 0); +uint32_t helper_fcmpq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + FloatRelation r =3D float128_compare_quiet(f128_in(src1), f128_in(src2= ), + &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 -GEN_FCMP_T(fcmps_fcc3, float32, 26, 0); -GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0); -GEN_FCMP(fcmpq_fcc3, float128, 26, 0); - -GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1); -GEN_FCMP_T(fcmped_fcc1, float64, 22, 1); -GEN_FCMP(fcmpeq_fcc1, float128, 22, 1); - -GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1); -GEN_FCMP_T(fcmped_fcc2, float64, 24, 1); -GEN_FCMP(fcmpeq_fcc2, float128, 24, 1); - -GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1); -GEN_FCMP_T(fcmped_fcc3, float64, 26, 1); -GEN_FCMP(fcmpeq_fcc3, float128, 26, 1); -#endif -#undef GEN_FCMP_T -#undef GEN_FCMP +uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) +{ + FloatRelation r =3D float128_compare(f128_in(src1), f128_in(src2), + &env->fp_status); + return finish_fcmp(env, r, GETPC()); +} =20 target_ulong cpu_get_fsr(CPUSPARCState *env) { target_ulong fsr =3D env->fsr | env->fsr_cexc_ftt; =20 + fsr |=3D env->fcc[0] << FSR_FCC0_SHIFT; +#ifdef TARGET_SPARC64 + fsr |=3D (uint64_t)env->fcc[1] << FSR_FCC1_SHIFT; + fsr |=3D (uint64_t)env->fcc[2] << FSR_FCC2_SHIFT; + fsr |=3D (uint64_t)env->fcc[3] << FSR_FCC3_SHIFT; +#endif + /* VER is kept completely separate until re-assembly. */ fsr |=3D env->def.fpu_version; =20 @@ -465,7 +432,7 @@ static void set_fsr_nonsplit(CPUSPARCState *env, target= _ulong fsr) { int rnd_mode; =20 - env->fsr =3D fsr & ~(FSR_VER_MASK | FSR_CEXC_MASK | FSR_FTT_MASK); + env->fsr =3D fsr & (FSR_RD_MASK | FSR_TEM_MASK | FSR_AEXC_MASK); =20 switch (fsr & FSR_RD_MASK) { case FSR_RD_NEAREST: @@ -488,10 +455,18 @@ static void set_fsr_nonsplit(CPUSPARCState *env, targ= et_ulong fsr) void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) { env->fsr_cexc_ftt =3D fsr & (FSR_CEXC_MASK | FSR_FTT_MASK); + + env->fcc[0] =3D extract32(fsr, FSR_FCC0_SHIFT, 2); +#ifdef TARGET_SPARC64 + env->fcc[1] =3D extract64(fsr, FSR_FCC1_SHIFT, 2); + env->fcc[2] =3D extract64(fsr, FSR_FCC2_SHIFT, 2); + env->fcc[3] =3D extract64(fsr, FSR_FCC3_SHIFT, 2); +#endif + set_fsr_nonsplit(env, fsr); } =20 -void helper_set_fsr_noftt(CPUSPARCState *env, target_ulong fsr) +void helper_set_fsr_nofcc_noftt(CPUSPARCState *env, uint32_t fsr) { env->fsr_cexc_ftt &=3D FSR_FTT_MASK; env->fsr_cexc_ftt |=3D fsr & FSR_CEXC_MASK; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cf8cfe5cc4..7df6f83b13 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -83,8 +83,6 @@ # define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) -# define FSR_LDXFSR_MASK 0 -# define FSR_LDXFSR_OLDMASK 0 # define MAXTL_MASK 0 #endif =20 @@ -130,6 +128,7 @@ static TCGv cpu_gsr; =20 /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; +static TCGv_i32 cpu_fcc[TARGET_FCCREGS]; =20 #define env_field_offsetof(X) offsetof(CPUSPARCState, X) #ifdef TARGET_SPARC64 @@ -719,159 +718,6 @@ static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 sr= c1, TCGv_i64 src2) #endif } =20 -// 1 -static void gen_op_eval_ba(TCGv dst) -{ - tcg_gen_movi_tl(dst, 1); -} - -// 0 -static void gen_op_eval_bn(TCGv dst) -{ - tcg_gen_movi_tl(dst, 0); -} - -/* - FPSR bit field FCC1 | FCC0: - 0 =3D - 1 < - 2 > - 3 unordered -*/ -static void gen_mov_reg_FCC0(TCGv reg, TCGv src, - unsigned int fcc_offset) -{ - tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); - tcg_gen_andi_tl(reg, reg, 0x1); -} - -static void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset) -{ - tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); - tcg_gen_andi_tl(reg, reg, 0x1); -} - -// !0: FCC0 | FCC1 -static void gen_op_eval_fbne(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_or_tl(dst, dst, t0); -} - -// 1 or 2: FCC0 ^ FCC1 -static void gen_op_eval_fblg(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_xor_tl(dst, dst, t0); -} - -// 1 or 3: FCC0 -static void gen_op_eval_fbul(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - gen_mov_reg_FCC0(dst, src, fcc_offset); -} - -// 1: FCC0 & !FCC1 -static void gen_op_eval_fbl(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_andc_tl(dst, dst, t0); -} - -// 2 or 3: FCC1 -static void gen_op_eval_fbug(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - gen_mov_reg_FCC1(dst, src, fcc_offset); -} - -// 2: !FCC0 & FCC1 -static void gen_op_eval_fbg(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_andc_tl(dst, t0, dst); -} - -// 3: FCC0 & FCC1 -static void gen_op_eval_fbu(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_and_tl(dst, dst, t0); -} - -// 0: !(FCC0 | FCC1) -static void gen_op_eval_fbe(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_or_tl(dst, dst, t0); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// 0 or 3: !(FCC0 ^ FCC1) -static void gen_op_eval_fbue(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_xor_tl(dst, dst, t0); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// 0 or 2: !FCC0 -static void gen_op_eval_fbge(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - gen_mov_reg_FCC0(dst, src, fcc_offset); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !1: !(FCC0 & !FCC1) -static void gen_op_eval_fbuge(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_andc_tl(dst, dst, t0); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// 0 or 1: !FCC1 -static void gen_op_eval_fble(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - gen_mov_reg_FCC1(dst, src, fcc_offset); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !2: !(!FCC0 & FCC1) -static void gen_op_eval_fbule(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_andc_tl(dst, t0, dst); - tcg_gen_xori_tl(dst, dst, 0x1); -} - -// !3: !(FCC0 & FCC1) -static void gen_op_eval_fbo(TCGv dst, TCGv src, unsigned int fcc_offset) -{ - TCGv t0 =3D tcg_temp_new(); - gen_mov_reg_FCC0(dst, src, fcc_offset); - gen_mov_reg_FCC1(t0, src, fcc_offset); - tcg_gen_and_tl(dst, dst, t0); - tcg_gen_xori_tl(dst, dst, 0x1); -} - static void finishing_insn(DisasContext *dc) { /* @@ -1096,82 +942,62 @@ static void gen_compare(DisasCompare *cmp, bool xcc,= unsigned int cond, =20 static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int = cond) { - unsigned int offset; - TCGv r_dst, fsr; + TCGv_i32 fcc =3D cpu_fcc[cc]; + TCGv_i32 c1 =3D fcc; + int c2 =3D 0; + TCGCond tcond; =20 - /* For now we still generate a straight boolean result. */ - cmp->cond =3D TCG_COND_NE; - cmp->c1 =3D r_dst =3D tcg_temp_new(); - cmp->c2 =3D 0; - - switch (cc) { - default: - case 0x0: - offset =3D 0; + /* + * FCC values: + * 0 =3D + * 1 < + * 2 > + * 3 unordered + */ + switch (cond & 7) { + case 0x0: /* fbn */ + tcond =3D TCG_COND_NEVER; break; - case 0x1: - offset =3D 32 - 10; + case 0x1: /* fbne : !0 */ + tcond =3D TCG_COND_NE; break; - case 0x2: - offset =3D 34 - 10; + case 0x2: /* fblg : 1 or 2 */ + /* fcc in {1,2} - 1 -> fcc in {0,1} */ + c1 =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(c1, fcc, -1); + c2 =3D 1; + tcond =3D TCG_COND_LEU; break; - case 0x3: - offset =3D 36 - 10; + case 0x3: /* fbul : 1 or 3 */ + c1 =3D tcg_temp_new_i32(); + tcg_gen_andi_i32(c1, fcc, 1); + tcond =3D TCG_COND_NE; + break; + case 0x4: /* fbl : 1 */ + c2 =3D 1; + tcond =3D TCG_COND_EQ; + break; + case 0x5: /* fbug : 2 or 3 */ + c2 =3D 2; + tcond =3D TCG_COND_GEU; + break; + case 0x6: /* fbg : 2 */ + c2 =3D 2; + tcond =3D TCG_COND_EQ; + break; + case 0x7: /* fbu : 3 */ + c2 =3D 3; + tcond =3D TCG_COND_EQ; break; } - - fsr =3D tcg_temp_new(); - tcg_gen_ld_tl(fsr, tcg_env, offsetof(CPUSPARCState, fsr)); - switch (cond) { - case 0x0: - gen_op_eval_bn(r_dst); - break; - case 0x1: - gen_op_eval_fbne(r_dst, fsr, offset); - break; - case 0x2: - gen_op_eval_fblg(r_dst, fsr, offset); - break; - case 0x3: - gen_op_eval_fbul(r_dst, fsr, offset); - break; - case 0x4: - gen_op_eval_fbl(r_dst, fsr, offset); - break; - case 0x5: - gen_op_eval_fbug(r_dst, fsr, offset); - break; - case 0x6: - gen_op_eval_fbg(r_dst, fsr, offset); - break; - case 0x7: - gen_op_eval_fbu(r_dst, fsr, offset); - break; - case 0x8: - gen_op_eval_ba(r_dst); - break; - case 0x9: - gen_op_eval_fbe(r_dst, fsr, offset); - break; - case 0xa: - gen_op_eval_fbue(r_dst, fsr, offset); - break; - case 0xb: - gen_op_eval_fbge(r_dst, fsr, offset); - break; - case 0xc: - gen_op_eval_fbuge(r_dst, fsr, offset); - break; - case 0xd: - gen_op_eval_fble(r_dst, fsr, offset); - break; - case 0xe: - gen_op_eval_fbule(r_dst, fsr, offset); - break; - case 0xf: - gen_op_eval_fbo(r_dst, fsr, offset); - break; + if (cond & 8) { + tcond =3D tcg_invert_cond(tcond); } + + cmp->cond =3D tcond; + cmp->c2 =3D c2; + cmp->c1 =3D tcg_temp_new(); + tcg_gen_extu_i32_tl(cmp->c1, c1); } =20 static bool gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) @@ -1261,148 +1087,6 @@ static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 s= rc) tcg_gen_concat_i64_i128(dst, l, h); } =20 -#ifdef TARGET_SPARC64 -static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmps(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmps_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmps_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmps_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmpd(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmpd_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmpd_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmpd_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmpq(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmpq_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmpq_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmpq_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmpes(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmpes_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmpes_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmpes_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmped(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmped_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmped_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmped_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) -{ - switch (fccno) { - case 0: - gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2); - break; - case 1: - gen_helper_fcmpeq_fcc1(tcg_env, r_rs1, r_rs2); - break; - case 2: - gen_helper_fcmpeq_fcc2(tcg_env, r_rs1, r_rs2); - break; - case 3: - gen_helper_fcmpeq_fcc3(tcg_env, r_rs1, r_rs2); - break; - } -} - -#else - -static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) -{ - gen_helper_fcmps(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) -{ - gen_helper_fcmpd(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) -{ - gen_helper_fcmpq(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) -{ - gen_helper_fcmpes(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) -{ - gen_helper_fcmped(tcg_env, r_rs1, r_rs2); -} - -static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) -{ - gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2); -} -#endif - static void gen_op_fpexception_im(DisasContext *dc, int ftt) { /* @@ -4400,11 +4084,10 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ= *a) return true; } =20 -static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop, - target_ulong new_mask, target_ulong old_mask) +static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) { TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); - TCGv tnew, told; + TCGv_i32 tmp; =20 if (addr =3D=3D NULL) { return false; @@ -4412,19 +4095,48 @@ static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *= a, MemOp mop, if (gen_trap_ifnofpu(dc)) { return true; } - tnew =3D tcg_temp_new(); - told =3D tcg_temp_new(); - tcg_gen_qemu_ld_tl(tnew, addr, dc->mem_idx, mop | MO_ALIGN); - tcg_gen_ld_tl(told, tcg_env, offsetof(CPUSPARCState, fsr)); - tcg_gen_andi_tl(tnew, tnew, new_mask); - tcg_gen_andi_tl(told, told, old_mask); - tcg_gen_or_tl(tnew, tnew, told); - gen_helper_set_fsr_noftt(tcg_env, tnew); + + tmp =3D tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN); + + tcg_gen_extract_i32(cpu_fcc[0], tmp, FSR_FCC0_SHIFT, 2); + /* LDFSR does not change FCC[1-3]. */ + + gen_helper_set_fsr_nofcc_noftt(tcg_env, tmp); return advance_pc(dc); } =20 -TRANS(LDFSR, ALL, do_ldfsr, a, MO_TEUL, FSR_LDFSR_MASK, FSR_LDFSR_OLDMASK) -TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_MASK, FSR_LDXFSR_OLDMAS= K) +static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a) +{ +#ifdef TARGET_SPARC64 + TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv_i64 t64; + TCGv_i32 lo, hi; + + if (addr =3D=3D NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + t64 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(t64, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN); + + lo =3D tcg_temp_new_i32(); + hi =3D cpu_fcc[3]; + tcg_gen_extr_i64_i32(lo, hi, t64); + tcg_gen_extract_i32(cpu_fcc[0], lo, FSR_FCC0_SHIFT, 2); + tcg_gen_extract_i32(cpu_fcc[1], hi, FSR_FCC1_SHIFT - 32, 2); + tcg_gen_extract_i32(cpu_fcc[2], hi, FSR_FCC2_SHIFT - 32, 2); + tcg_gen_extract_i32(cpu_fcc[3], hi, FSR_FCC3_SHIFT - 32, 2); + + gen_helper_set_fsr_nofcc_noftt(tcg_env, lo); + return advance_pc(dc); +#else + return false; +#endif +} =20 static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) { @@ -5075,9 +4787,9 @@ static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, = bool e) src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); if (e) { - gen_op_fcmpes(a->cc, src1, src2); + gen_helper_fcmpes(cpu_fcc[a->cc], tcg_env, src1, src2); } else { - gen_op_fcmps(a->cc, src1, src2); + gen_helper_fcmps(cpu_fcc[a->cc], tcg_env, src1, src2); } return advance_pc(dc); } @@ -5099,9 +4811,9 @@ static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, = bool e) src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); if (e) { - gen_op_fcmped(a->cc, src1, src2); + gen_helper_fcmped(cpu_fcc[a->cc], tcg_env, src1, src2); } else { - gen_op_fcmpd(a->cc, src1, src2); + gen_helper_fcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); } return advance_pc(dc); } @@ -5126,9 +4838,9 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, = bool e) src1 =3D gen_load_fpr_Q(dc, a->rs1); src2 =3D gen_load_fpr_Q(dc, a->rs2); if (e) { - gen_op_fcmpeq(a->cc, src1, src2); + gen_helper_fcmpeq(cpu_fcc[a->cc], tcg_env, src1, src2); } else { - gen_op_fcmpq(a->cc, src1, src2); + gen_helper_fcmpq(cpu_fcc[a->cc], tcg_env, src1, src2); } return advance_pc(dc); } @@ -5334,6 +5046,18 @@ void sparc_tcg_init(void) "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", }; =20 + static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[= ] =3D { +#ifdef TARGET_SPARC64 + { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, + { &cpu_fcc[0], offsetof(CPUSPARCState, fcc[0]), "fcc0" }, + { &cpu_fcc[1], offsetof(CPUSPARCState, fcc[1]), "fcc1" }, + { &cpu_fcc[2], offsetof(CPUSPARCState, fcc[2]), "fcc2" }, + { &cpu_fcc[3], offsetof(CPUSPARCState, fcc[3]), "fcc3" }, +#else + { &cpu_fcc[0], offsetof(CPUSPARCState, fcc[0]), "fcc" }, +#endif + }; + static const struct { TCGv *ptr; int off; const char *name; } rtl[] = =3D { #ifdef TARGET_SPARC64 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" }, @@ -5357,6 +5081,10 @@ void sparc_tcg_init(void) offsetof(CPUSPARCState, regwptr), "regwptr"); =20 + for (i =3D 0; i < ARRAY_SIZE(r32); ++i) { + *r32[i].ptr =3D tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i]= .name); + } + for (i =3D 0; i < ARRAY_SIZE(rtl); ++i) { *rtl[i].ptr =3D tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].nam= e); } @@ -5379,11 +5107,6 @@ void sparc_tcg_init(void) offsetof(CPUSPARCState, fpr[i]= ), fregnames[i]); } - -#ifdef TARGET_SPARC64 - cpu_fprs =3D tcg_global_mem_new_i32(tcg_env, - offsetof(CPUSPARCState, fprs), "fprs= "); -#endif } =20 void sparc_restore_state_to_opc(CPUState *cs, --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853530; cv=none; d=zohomail.com; s=zohoarc; b=B6cAkxTPeyCAJuiZ7UWqCZYdQ35hGgjzYDINMLtWlLSNDROJjGeNuSWZ1kFaCaf+CBB/zYjgM2hV7m+kASFnAMopguI4xkH2KwteySzCgZVBIe6BJC8LPaHBm+NGjd5XFe+KM+T1nMLEv1PNEZekheDTY6VoZkPmMcJKODtO5yM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853530; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id je5-20020a170903264500b001d8a80cbb15sm752059plb.238.2024.02.01.21.55.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:55:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706853348; x=1707458148; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oSDPCFSlupjS1LwiiY/IHM0gph76gQ4U11W6UuPY57o=; b=EiSvrjChgEw66HKwtucflOnIFKnZvaqkI7BGxUqbbKkRBwez3KMCgDAgi8bvpdPwbX iLtZ/x/YxRT6dk44mASsFc1R3B8vBgUmOxABV+hZ/yoSG5vKEOeW9krZk/NNm6By+7II 4iqY21z1KEtd9nuVm7M7oZ0PUKijo+ylLiIYkY3HviwftDr1O2grUg6RmKW9HqZ/v07I 4PgVj7l09zPLQHzlidWAQfDxWnv6KOD3kGClvXAuJEiAUpVQp8ENwOxbPa7Ci1lWNQID RtLUn2+snAwmBbVRlJZb3bD+tDhXwoI98iBEcAWwjC7WF7ufxMmmQjg814VfOui030qc Yr7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706853348; x=1707458148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oSDPCFSlupjS1LwiiY/IHM0gph76gQ4U11W6UuPY57o=; b=by83GW3LOnISXLLSD3ODO936amOATn6CbWCEBhGiYqHKM4QHKlsdsjixE1s/b9gzjV wjDAQv7lDS/wUiRu/HWT6Rc1ahsBtl9klsGZaXEYE0/vpcmxhtlEDDiWzsI6fl6V3oHL 1by3SHqaMdWtP2hoHLkoMd9QGMcm94v5hUETLLrD68pSliYY5aLTrGqMn/zGrIUX63YU VdPNBmt1AeB44AYfMRKkWsBOjsjEJxbdU3AzMe3cTaMQQPAXMBN9o4m1fpVfMHiYifuL mbcFZ0jjnbybZYimBt570ndBTfSIGWcHMApdrcP8DuRoXl1OC935eYmEtpG0s3VBxoS9 683Q== X-Gm-Message-State: AOJu0Yw8GvRrdAe6GHNi2i5rpCPBpWaE5/9AaCh39zHBpWf1fayP0Y7v m88oDeJY5ptcw2k4/17vT+8p41MyPuq82fhUXBV4x+7eqXuBa3TRGbqAmY6PZmJ8K9xfzffNe5T 1lac= X-Google-Smtp-Source: AGHT+IG6soDpuiO/GvCVxZ7Kz2Ff+edkprRRBUfnm/6VuhO1MPmP7zeJGhyrZMgdxQ/YjMoLh4c8pQ== X-Received: by 2002:a17:903:120d:b0:1d7:587f:3748 with SMTP id l13-20020a170903120d00b001d7587f3748mr8137875plh.63.1706853348069; Thu, 01 Feb 2024 21:55:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 57/57] target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK Date: Fri, 2 Feb 2024 15:50:36 +1000 Message-Id: <20240202055036.684176-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1706853531865100008 Content-Type: text/plain; charset="utf-8" These macros are no longer used. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-23-richard.henderson@linaro.org> --- target/sparc/cpu.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 986c7217ed..edf46b387e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -202,13 +202,6 @@ enum { #define FSR_FTT1 (1ULL << 15) #define FSR_FTT0 (1ULL << 14) #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) -#ifdef TARGET_SPARC64 -#define FSR_FTT_NMASK 0xfffffffffffe3fffULL -#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL -#else -#define FSR_FTT_NMASK 0xfffe3fffULL -#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL -#endif #define FSR_FTT_IEEE_EXCP (1ULL << 14) #define FSR_FTT_UNIMPFPOP (3ULL << 14) #define FSR_FTT_SEQ_ERROR (4ULL << 14) --=20 2.34.1 From nobody Tue Nov 26 12:45:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706853382; cv=none; d=zohomail.com; s=zohoarc; b=BMTeCdhqlwjCDdX3ZMeP8lDizI6n7OE/I4i8qrkFgjOwCBfi4pdEkPOWcCY568Vl73ZnIBYjZqVojgH0s1Myhyd2me+pP51ffm6FBjOedUKD/reRl+ipWAyLhzrMSO/Wvn8HBtxYt8LvHpXnDTqCKxp/N47L26Ws9x83zOAwV+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706853382; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Kq0J8Afnqo7enZSunt87RCQsJ4GxKCY2HEoeL1qsLBQ=; b=c6ZYXqUT5FrUMuRwSUX/b5A3Lb8+iyp7NtfjBVg1B7UpTud4Tbd9/N9li6P+PqTRLLVrfoGhLMKYym/c8DbKxGiRWN6W173h0yAxI6HpE/aAMComS/fJoxIKcnVAUGRarz+V4JrB59N4hcD5P9aOM02UMoVmgbJua6HMzz0gfw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706853382344767.3761953018046; Thu, 1 Feb 2024 21:56:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVmRt-00012m-Md; Fri, 02 Feb 2024 00:50:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVmRs-00012J-4v for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:50:48 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVmRq-0001b8-Gl for qemu-devel@nongnu.org; Fri, 02 Feb 2024 00:50:47 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6ddb807e23bso1212472b3a.0 for ; Thu, 01 Feb 2024 21:50:46 -0800 (PST) Received: from stoup.. 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This fixes gcc's 30_threads/thread/native_handle/cancel.cc. Cc: qemu-stable@nongnu.org Fixes: ee95fae075c6 ("linux-user/aarch64: Add vdso") Resolves: https://linaro.atlassian.net/browse/GNU-974 Signed-off-by: Richard Henderson --- linux-user/aarch64/vdso-be.so | Bin 3216 -> 3224 bytes linux-user/aarch64/vdso-le.so | Bin 3216 -> 3224 bytes linux-user/aarch64/vdso.S | 4 ++++ 3 files changed, 4 insertions(+) diff --git a/linux-user/aarch64/vdso-be.so b/linux-user/aarch64/vdso-be.so index 6084f3d1a701316004894fcdd739c4e1e0463b68..808206ade824b09d786f6cc34f7= cddf80b63130e 100755 GIT binary patch delta 121 zcmbOrIYV-SKI4pu2Kk&{7{Gw#%fuBAMC1c?^>~k}v|avdxNjSSLfftVb3bgJ!|2S& z_-6A1CJrVZc?IUH8G;R$7#SF@Om<{a*v!K!&BXX-vIe^~TWO|cva$K*Om;sOMw`hy ZxXl@VO#Z-a&zLdUfXALuXmSCM0s#EKC)of1 delta 116 zcmbOsIYDxQKI4Rm2Kk&H7{Gw#!^9O2L>8U?-5V_M@!kH(Sx4vJn|*ujLPgija~Pc& z8DDIEz{J5c`3;N8W)W6tCdL<&4cM*OEF8_CVnO!c?IUH8G;R$7#SF@Om<{a*v!K!!o>JyvLd?^n`3BUW_royOm=3Dq`Mw`hS dxy>1WOn%92&zLb;lgFM@hy!9z%j7~Xc>tTxDQW-! delta 108 zcmbOsIYDxQ2IGW@n)#d`SQx