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a="402676996" X-IronPort-AV: E=Sophos;i="6.05,234,1701158400"; d="scan'208";a="402676996" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,234,1701158400"; d="scan'208";a="4443418" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, peterx@redhat.com, jasowang@redhat.com, mst@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, kevin.tian@intel.com, yi.l.liu@intel.com, yi.y.sun@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv2 17/18] intel_iommu: Use mgaw instead of s->aw_bits Date: Thu, 1 Feb 2024 15:28:17 +0800 Message-Id: <20240201072818.327930-18-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240201072818.327930-1-zhenzhong.duan@intel.com> References: <20240201072818.327930-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.120; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.292, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1706772806208100003 Content-Type: text/plain; charset="utf-8" Because vIOMMU mgaw can be updated based on host IOMMU mgaw, s->aw_bits does't necessarily represent the final mgaw now but the mgaw field in s->cap does. Replace reference to s->aw_bits with a MACRO S_AW_BITS to fetch mgaw from s->cap. There are two exceptions on this, aw_bits value sanity check and s->cap initialization. ACPI DMAR table is also updated with right mgaw value. Signed-off-by: Zhenzhong Duan --- hw/i386/acpi-build.c | 3 ++- hw/i386/intel_iommu.c | 44 ++++++++++++++++++++++--------------------- 2 files changed, 25 insertions(+), 22 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index edc979379c..6467157686 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2159,7 +2159,8 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker= , const char *oem_id, =20 acpi_table_begin(&table, table_data); /* Host Address Width */ - build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); + build_append_int_noprefix(table_data, + VTD_MGAW_FROM_CAP(intel_iommu->cap), 1); build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ =20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 409f8a59c3..72cc8b2c71 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -41,6 +41,8 @@ #include "migration/vmstate.h" #include "trace.h" =20 +#define S_AW_BITS (VTD_MGAW_FROM_CAP(s->cap) + 1) + /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK) @@ -1409,13 +1411,13 @@ static int vtd_root_entry_rsvd_bits_check(IntelIOMM= UState *s, { /* Legacy Mode reserved bits check */ if (!s->root_scalable && - (re->hi || (re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)))) + (re->hi || (re->lo & VTD_ROOT_ENTRY_RSVD(S_AW_BITS)))) goto rsvd_err; =20 /* Scalable Mode reserved bits check */ if (s->root_scalable && - ((re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)) || - (re->hi & VTD_ROOT_ENTRY_RSVD(s->aw_bits)))) + ((re->lo & VTD_ROOT_ENTRY_RSVD(S_AW_BITS)) || + (re->hi & VTD_ROOT_ENTRY_RSVD(S_AW_BITS)))) goto rsvd_err; =20 return 0; @@ -1432,7 +1434,7 @@ static inline int vtd_context_entry_rsvd_bits_check(I= ntelIOMMUState *s, { if (!s->root_scalable && (ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI || - ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) { + ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(S_AW_BITS))) { error_report_once("%s: invalid context entry: hi=3D%"PRIx64 ", lo=3D%"PRIx64" (reserved nonzero)", __func__, ce->hi, ce->lo); @@ -1440,7 +1442,7 @@ static inline int vtd_context_entry_rsvd_bits_check(I= ntelIOMMUState *s, } =20 if (s->root_scalable && - (ce->val[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(s->aw_bits) || + (ce->val[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(S_AW_BITS) || ce->val[1] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 || ce->val[2] || ce->val[3])) { @@ -1571,7 +1573,7 @@ static int vtd_sync_shadow_page_table_range(VTDAddres= sSpace *vtd_as, .hook_fn =3D vtd_sync_shadow_page_hook, .private =3D (void *)&vtd_as->iommu, .notify_unmap =3D true, - .aw =3D s->aw_bits, + .aw =3D S_AW_BITS, .as =3D vtd_as, .domain_id =3D vtd_get_domain_id(s, ce, vtd_as->pasid), }; @@ -1990,7 +1992,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, } =20 ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level, - &reads, &writes, s->aw_bits, pasid); + &reads, &writes, S_AW_BITS, pasid); if (ret_fr) { vtd_report_fault(s, -ret_fr, is_fpd_set, source_id, addr, is_write, pasid !=3D PCI_NO_PASID, pasid); @@ -2004,7 +2006,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, out: vtd_iommu_unlock(s); entry->iova =3D addr & page_mask; - entry->translated_addr =3D vtd_get_slpte_addr(slpte, s->aw_bits) & pag= e_mask; + entry->translated_addr =3D vtd_get_slpte_addr(slpte, S_AW_BITS) & page= _mask; entry->addr_mask =3D ~page_mask; entry->perm =3D access_flags; return true; @@ -2021,7 +2023,7 @@ error: static void vtd_root_table_setup(IntelIOMMUState *s) { s->root =3D vtd_get_quad_raw(s, DMAR_RTADDR_REG); - s->root &=3D VTD_RTADDR_ADDR_MASK(s->aw_bits); + s->root &=3D VTD_RTADDR_ADDR_MASK(S_AW_BITS); =20 vtd_update_scalable_state(s); =20 @@ -2039,7 +2041,7 @@ static void vtd_interrupt_remap_table_setup(IntelIOMM= UState *s) uint64_t value =3D 0; value =3D vtd_get_quad_raw(s, DMAR_IRTA_REG); s->intr_size =3D 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1); - s->intr_root =3D value & VTD_IRTA_ADDR_MASK(s->aw_bits); + s->intr_root =3D value & VTD_IRTA_ADDR_MASK(S_AW_BITS); s->intr_eime =3D value & VTD_IRTA_EIME; =20 /* Notify global invalidation */ @@ -2322,7 +2324,7 @@ static void vtd_handle_gcmd_qie(IntelIOMMUState *s, b= ool en) trace_vtd_inv_qi_enable(en); =20 if (en) { - s->iq =3D iqa_val & VTD_IQA_IQA_MASK(s->aw_bits); + s->iq =3D iqa_val & VTD_IQA_IQA_MASK(S_AW_BITS); /* 2^(x+8) entries */ s->iq_size =3D 1UL << ((iqa_val & VTD_IQA_QS) + 8 - (s->iq_dw ? 1 = : 0)); s->qi_enabled =3D true; @@ -3958,12 +3960,12 @@ static void vtd_address_space_unmap(VTDAddressSpace= *as, IOMMUNotifier *n) * VT-d spec), otherwise we need to consider overflow of 64 bits. */ =20 - if (end > VTD_ADDRESS_SIZE(s->aw_bits) - 1) { + if (end > VTD_ADDRESS_SIZE(S_AW_BITS) - 1) { /* * Don't need to unmap regions that is bigger than the whole * VT-d supported address space size */ - end =3D VTD_ADDRESS_SIZE(s->aw_bits) - 1; + end =3D VTD_ADDRESS_SIZE(S_AW_BITS) - 1; } =20 assert(start <=3D end); @@ -3971,7 +3973,7 @@ static void vtd_address_space_unmap(VTDAddressSpace *= as, IOMMUNotifier *n) =20 while (remain >=3D VTD_PAGE_SIZE) { IOMMUTLBEvent event; - uint64_t mask =3D dma_aligned_pow2_mask(start, end, s->aw_bits); + uint64_t mask =3D dma_aligned_pow2_mask(start, end, S_AW_BITS); uint64_t size =3D mask + 1; =20 assert(size); @@ -4050,7 +4052,7 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iommu= _mr, IOMMUNotifier *n) .hook_fn =3D vtd_replay_hook, .private =3D (void *)n, .notify_unmap =3D false, - .aw =3D s->aw_bits, + .aw =3D S_AW_BITS, .as =3D vtd_as, .domain_id =3D vtd_get_domain_id(s, &ce, vtd_as->pasid), }; @@ -4153,15 +4155,15 @@ static void vtd_init(IntelIOMMUState *s) * Rsvd field masks for spte */ vtd_spte_rsvd[0] =3D ~0ULL; - vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(S_AW_BITS, x86_iommu->dt_supported); - vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(S_AW_BITS); + vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(S_AW_BITS); + vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(S_AW_BITS); =20 - vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(S_AW_BITS, x86_iommu->dt_supporte= d); - vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(S_AW_BITS, x86_iommu->dt_supporte= d); =20 if (s->scalable_mode || s->snoop_control) { --=20 2.34.1