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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Babu Moger , Xiaoyao Li , Zhenyu Wang , Zhuocheng Ding , Yongwei Ma , Zhao Liu Subject: [PATCH v8 19/21] i386: Add cache topology info in CPUCacheInfo Date: Wed, 31 Jan 2024 18:13:48 +0800 Message-Id: <20240131101350.109512-20-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101350.109512-1-zhao1.liu@linux.intel.com> References: <20240131101350.109512-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.292, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1706695616455100007 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Currently, by default, the cache topology is encoded as: 1. i/d cache is shared in one core. 2. L2 cache is shared in one core. 3. L3 cache is shared in one die. This default general setting has caused a misunderstanding, that is, the cache topology is completely equated with a specific cpu topology, such as the connection between L2 cache and core level, and the connection between L3 cache and die level. In fact, the settings of these topologies depend on the specific platform and are not static. For example, on Alder Lake-P, every four Atom cores share the same L2 cache. Thus, we should explicitly define the corresponding cache topology for different cache models to increase scalability. Except legacy_l2_cache_cpuid2 (its default topo level is CPU_TOPO_LEVEL_UNKNOW), explicitly set the corresponding topology level for all other cache models. In order to be compatible with the existing cache topology, set the CPU_TOPO_LEVEL_CORE level for the i/d cache, set the CPU_TOPO_LEVEL_CORE level for L2 cache, and set the CPU_TOPO_LEVEL_DIE level for L3 cache. The field for CPUID[4].EAX[bits 25:14] or CPUID[0x8000001D].EAX[bits 25:14] will be set based on CPUCacheInfo.share_level. Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * Fixed cache topology uninitialization bugs for some AMD CPUs. (Babu) * Moved the CPUTopoLevel enumeration definition to the previous 0x1f rework patch. Changes since v1: * Added the prefix "CPU_TOPO_LEVEL_*" for CPU topology level names. (Yanan) * (Revert, pls refer "i386: Decouple CPUID[0x1F] subleaf with specific topology level") Renamed the "INVALID" level to CPU_TOPO_LEVEL_UNKNOW. (Yanan) --- target/i386/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 7 +++++++ 2 files changed, 43 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6af734dd73c8..f167df4f6df1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -554,6 +554,7 @@ static CPUCacheInfo legacy_l1d_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -568,6 +569,7 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* L1 instruction cache: */ @@ -581,6 +583,7 @@ static CPUCacheInfo legacy_l1i_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -595,6 +598,7 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* Level 2 unified cache: */ @@ -608,6 +612,7 @@ static CPUCacheInfo legacy_l2_cache =3D { .sets =3D 4096, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -617,6 +622,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 =3D { .size =3D 2 * MiB, .line_size =3D 64, .associativity =3D 8, + .share_level =3D CPU_TOPO_LEVEL_INVALID, }; =20 =20 @@ -630,6 +636,7 @@ static CPUCacheInfo legacy_l2_cache_amd =3D { .associativity =3D 16, .sets =3D 512, .partitions =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* Level 3 unified cache: */ @@ -645,6 +652,7 @@ static CPUCacheInfo legacy_l3_cache =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }; =20 /* TLB definitions: */ @@ -1942,6 +1950,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -1954,6 +1963,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1964,6 +1974,7 @@ static const CPUCaches epyc_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1977,6 +1988,7 @@ static const CPUCaches epyc_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -1992,6 +2004,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2004,6 +2017,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2014,6 +2028,7 @@ static CPUCaches epyc_v4_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2027,6 +2042,7 @@ static CPUCaches epyc_v4_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2042,6 +2058,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2054,6 +2071,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2064,6 +2082,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2077,6 +2096,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2092,6 +2112,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2104,6 +2125,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2114,6 +2136,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2127,6 +2150,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2142,6 +2166,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2154,6 +2179,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2164,6 +2190,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2177,6 +2204,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2192,6 +2220,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2204,6 +2233,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2214,6 +2244,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2227,6 +2258,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2242,6 +2274,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2254,6 +2287,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2264,6 +2298,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .partitions =3D 1, .sets =3D 2048, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2277,6 +2312,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 29837ca69859..5ddd08950431 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1583,6 +1583,13 @@ typedef struct CPUCacheInfo { * address bits. CPUID[4].EDX[bit 2]. */ bool complex_indexing; + + /* + * Cache Topology. The level that cache is shared in. + * Used to encode CPUID[4].EAX[bits 25:14] or + * CPUID[0x8000001D].EAX[bits 25:14]. + */ + enum CPUTopoLevel share_level; } CPUCacheInfo; =20 =20 --=20 2.34.1