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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Babu Moger , Xiaoyao Li , Zhenyu Wang , Zhuocheng Ding , Yongwei Ma , Zhao Liu Subject: [PATCH v8 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Date: Wed, 31 Jan 2024 18:13:39 +0800 Message-Id: <20240131101350.109512-11-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101350.109512-1-zhao1.liu@linux.intel.com> References: <20240131101350.109512-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.7; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.292, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1706695337601100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared by Intel and AMD CPUs. But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU (in CPUID[0x80000026]) have the different definitions with different enumeration values. Though CPUID[0x80000026] hasn't been implemented in QEMU, to avoid possible misunderstanding, split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] and introduce CPUID[0x1F]-specific topology types. Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Changes since v3: * New commit to prepare to refactor CPUID[0x1F] encoding. --- target/i386/cpu.c | 14 +++++++------- target/i386/cpu.h | 13 +++++++++---- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 607d8eff017b..4e5feb153152 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6257,17 +6257,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 0: *eax =3D apicid_core_offset(&topo_info); *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_CORE << 8; break; default: *eax =3D 0; *ebx =3D 0; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |=3D CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; } =20 assert(!(*eax & ~0x1f)); @@ -6292,22 +6292,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 0: *eax =3D apicid_core_offset(&topo_info); *ebx =3D topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_SMT << 8; break; case 1: *eax =3D apicid_die_offset(&topo_info); *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_CORE << 8; break; case 2: *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D threads_per_pkg; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_DIE << 8; break; default: *eax =3D 0; *ebx =3D 0; - *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + *ecx |=3D CPUID_1F_ECX_TOPO_LEVEL_INVALID << 8; } assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f341affd5a59..8a7450f265a1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1010,10 +1010,15 @@ uint64_t x86_cpu_get_supported_feature_word(Feature= Word w, #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ =20 /* CPUID[0xB].ECX level types */ -#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) -#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) -#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) -#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) +#define CPUID_B_ECX_TOPO_LEVEL_INVALID 0 +#define CPUID_B_ECX_TOPO_LEVEL_SMT 1 +#define CPUID_B_ECX_TOPO_LEVEL_CORE 2 + +/* COUID[0x1F].ECX level types */ +#define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID +#define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT +#define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE +#define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 =20 /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0) --=20 2.34.1