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Wed, 31 Jan 2024 00:51:16 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCW3EdcYwuOOtWQtQOtDwqZxAM0tPC7i5yjZvXVtPCmGM5zroGQ5QxMPAd8VDCNaWArftqPz19sceHdgvvuBamLkPnf7BQtlxho= From: =?UTF-8?q?Cl=C3=A9ment=20Chigot?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Cl=C3=A9ment=20Chigot?= , Frederic Konrad Subject: [PATCH v3 7/9] leon3: implement multiprocessor Date: Wed, 31 Jan 2024 09:50:45 +0100 Message-Id: <20240131085047.18458-8-chigot@adacore.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240131085047.18458-1-chigot@adacore.com> References: <20240131085047.18458-1-chigot@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=chigot@adacore.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @adacore.com) X-ZM-MESSAGEID: 1706691215010100001 This allows to register more than one CPU on the leon3_generic machine. Co-developed-by: Frederic Konrad Signed-off-by: Cl=C3=A9ment Chigot --- hw/sparc/leon3.c | 98 ++++++++++++++++++++++++++++++++++-------------- 1 file changed, 70 insertions(+), 28 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 317eb57336..252aff72cd 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -54,6 +54,8 @@ #define LEON3_PROM_OFFSET (0x00000000) #define LEON3_RAM_OFFSET (0x40000000) =20 +#define MAX_CPUS 4 + #define LEON3_UART_OFFSET (0x80000100) #define LEON3_UART_IRQ (3) =20 @@ -67,8 +69,11 @@ #define LEON3_AHB_PNP_OFFSET (0xFFFFF000) =20 typedef struct ResetData { - SPARCCPU *cpu; - uint32_t entry; /* save kernel entry in case of reset */ + struct CPUResetData { + int id; + SPARCCPU *cpu; + } info[MAX_CPUS]; + uint32_t entry; /* save kernel entry in case of reset */ } ResetData; =20 static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) @@ -124,17 +129,19 @@ static void write_bootloader(CPUSPARCState *env, uint= 8_t *base, stl_p(p++, 0x01000000); /* nop */ } =20 -static void main_cpu_reset(void *opaque) +static void leon3_cpu_reset(void *opaque) { - ResetData *s =3D (ResetData *)opaque; - CPUState *cpu =3D CPU(s->cpu); - CPUSPARCState *env =3D &s->cpu->env; + struct CPUResetData *info =3D (struct CPUResetData *) opaque; + int id =3D info->id; + ResetData *s =3D (ResetData *)DO_UPCAST(ResetData, info[id], info); + CPUState *cpu =3D CPU(s->info[id].cpu); + CPUSPARCState *env =3D cpu_env(cpu); =20 cpu_reset(cpu); =20 - cpu->halted =3D 0; - env->pc =3D s->entry; - env->npc =3D s->entry + 4; + cpu->halted =3D cpu->cpu_index !=3D 0; + env->pc =3D s->entry; + env->npc =3D s->entry + 4; } =20 static void leon3_cache_control_int(CPUSPARCState *env) @@ -168,8 +175,8 @@ static void leon3_cache_control_int(CPUSPARCState *env) =20 static void leon3_irq_ack(CPUSPARCState *env, int intno) { - /* No SMP support yet, only CPU #0 available so far. */ - grlib_irqmp_ack(env->irq_manager, 0, intno); + CPUState *cpu =3D CPU(env_cpu(env)); + grlib_irqmp_ack(env->irq_manager, cpu->cpu_index, intno); } =20 /* @@ -211,6 +218,19 @@ static void leon3_set_pil_in(void *opaque, int n, int = level) } } =20 +static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data) +{ + cpu->halted =3D 0; +} + +static void leon3_start_cpu(void *opaque, int n, int level) +{ + CPUState *cs =3D CPU(opaque); + + assert(level =3D=3D 1); + async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL); +} + static void leon3_irq_manager(CPUSPARCState *env, int intno) { leon3_irq_ack(env, intno); @@ -236,16 +256,20 @@ static void leon3_generic_hw_init(MachineState *machi= ne) AHBPnp *ahb_pnp; APBPnp *apb_pnp; =20 - /* Init CPU */ - cpu =3D SPARC_CPU(cpu_create(machine->cpu_type)); - env =3D &cpu->env; + reset_info =3D g_malloc0(sizeof(ResetData)); =20 - cpu_sparc_set_id(env, 0); + for (i =3D 0; i < machine->smp.cpus; i++) { + /* Init CPU */ + cpu =3D SPARC_CPU(cpu_create(machine->cpu_type)); + env =3D &cpu->env; =20 - /* Reset data */ - reset_info =3D g_new0(ResetData, 1); - reset_info->cpu =3D cpu; - qemu_register_reset(main_cpu_reset, reset_info); + cpu_sparc_set_id(env, i); + + /* Reset data */ + reset_info->info[i].id =3D i; + reset_info->info[i].cpu =3D cpu; + qemu_register_reset(leon3_cpu_reset, &reset_info->info[i]); + } =20 ahb_pnp =3D GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP)); sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal); @@ -263,14 +287,28 @@ static void leon3_generic_hw_init(MachineState *machi= ne) =20 /* Allocate IRQ manager */ irqmpdev =3D qdev_new(TYPE_GRLIB_IRQMP); + object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus, + &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal); - qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in, - env, "pil", 1); - qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0, - qdev_get_gpio_in_named(DEVICE(cpu), "pil",= 0)); + + for (i =3D 0; i < machine->smp.cpus; i++) { + cpu =3D reset_info->info[i].cpu; + env =3D &cpu->env; + qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_start_cpu, + cpu, "start_cpu", 1); + qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i, + qdev_get_gpio_in_named(DEVICE(cpu), + "start_cpu", 0)= ); + qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in, + env, "pil", 1); + qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i, + qdev_get_gpio_in_named(DEVICE(cpu), + "pil", 0)); + env->irq_manager =3D irqmpdev; + env->qemu_irq_ack =3D leon3_irq_manager; + } + sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET); - env->irq_manager =3D irqmpdev; - env->qemu_irq_ack =3D leon3_irq_manager; grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF, GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV, 2, 0, GRLIB_APBIO_AREA); @@ -344,10 +382,13 @@ static void leon3_generic_hw_init(MachineState *machi= ne) uint8_t *bootloader_entry; =20 bootloader_entry =3D memory_region_get_ram_ptr(prom); - write_bootloader(env, bootloader_entry, entry); - env->pc =3D LEON3_PROM_OFFSET; - env->npc =3D LEON3_PROM_OFFSET + 4; + write_bootloader(&reset_info->info[0].cpu->env, bootloader_ent= ry, + entry); reset_info->entry =3D LEON3_PROM_OFFSET; + for (i =3D 0; i < machine->smp.cpus; i++) { + reset_info->info[i].cpu->env.pc =3D LEON3_PROM_OFFSET; + reset_info->info[i].cpu->env.npc =3D LEON3_PROM_OFFSET + 4; + } } } =20 @@ -386,6 +427,7 @@ static void leon3_generic_machine_init(MachineClass *mc) mc->init =3D leon3_generic_hw_init; mc->default_cpu_type =3D SPARC_CPU_TYPE_NAME("LEON3"); mc->default_ram_id =3D "leon3.ram"; + mc->max_cpus =3D MAX_CPUS; } =20 DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init) --=20 2.25.1